On Mon, Mar 06, 2023 at 03:17:50PM -0800, Matt Roper wrote:
On Mon, Mar 06, 2023 at 12:49:54PM -0800, Lucas De Marchi wrote:
dg1_ctx_workarounds_init() is DG1-only, while
gen12_ctx_workarounds_init() is shared with other platforms. Move the
workaround to the former so there is no additional platform check
needed.
Signed-off-by: Lucas De Marchi <lucas.demar...@intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 9 +++------
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 389bfcd299af..f68fe64f63a6 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -707,8 +707,6 @@ static void gen12_ctx_gt_tuning_init(struct intel_engine_cs
*engine,
static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
{
- struct drm_i915_private *i915 = engine->i915;
-
gen12_ctx_gt_tuning_init(engine, wal);
/*
@@ -742,10 +740,6 @@ static void gen12_ctx_workarounds_init(struct
intel_engine_cs *engine,
FF_MODE2_GS_TIMER_MASK,
FF_MODE2_GS_TIMER_224,
0, false);
-
- if (!IS_DG1(i915))
I think you missed the "!" here. I.e., this workaround applies to all
the "gen12" platforms *except* DG1.
oops, thanks for catching that. I'll drop this last patch.
Lucas De Marchi
Matt
- /* Wa_1806527549 */
- wa_masked_en(wal, HIZ_CHICKEN, HZ_DEPTH_TEST_LE_GE_OPT_DISABLE);
}
static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine,
@@ -760,6 +754,9 @@ static void dg1_ctx_workarounds_init(struct intel_engine_cs
*engine,
/* Wa_22010493298 */
wa_masked_en(wal, HIZ_CHICKEN,
DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE);
+
+ /* Wa_1806527549 */
+ wa_masked_en(wal, HIZ_CHICKEN, HZ_DEPTH_TEST_LE_GE_OPT_DISABLE);
}
static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine,
--
2.39.0
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
