On Wed, Jan 22, 2014 at 10:32:04PM +0100, Daniel Vetter wrote:
> At least I couldn't find it in the Haswell Bspec any more and we've
> tried to test-boot a Haswell machine with num_pipes forced to 0 (i.e.
> hit the PCH_NOP path) and the unclaimed register logic complained.
>
> So restrict this dance to just ivb platforms.
>
> v2: Art pointed out that the bits simply moved on hsw+
>
> Cc: Arthur Ranyan <arthur.j.run...@intel.com>
> Cc: Dave Airlie <airl...@gmail.com>
> Signed-off-by: Daniel Vetter <daniel.vet...@ffwll.ch>
> ---
> drivers/gpu/drm/i915/i915_gem.c | 12 +++++++++---
> drivers/gpu/drm/i915/i915_reg.h | 2 ++
> 2 files changed, 11 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 32636a470367..17b094653621 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -4496,9 +4496,15 @@ i915_gem_init_hw(struct drm_device *dev)
> LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
>
> if (HAS_PCH_NOP(dev)) {
> - u32 temp = I915_READ(GEN7_MSG_CTL);
> - temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
> - I915_WRITE(GEN7_MSG_CTL, temp);
> + if (IS_IVYBRIDGE(dev)) {
> + u32 temp = I915_READ(GEN7_MSG_CTL);
> + temp &= ~(WAIT_FOR_PCH_FLR_ACK |
> WAIT_FOR_PCH_RESET_ACK);
> + I915_WRITE(GEN7_MSG_CTL, temp);
> + } else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) {
Increase subtlety with } else if (INTEL_INFO(dev)->gen >= 7) {
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
