>-----Original Message-----
>From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch]
>Sent: Wednesday, January 22, 2014 2:40 PM
>To: Intel Graphics Development
>Cc: Daniel Vetter; Chris Wilson; Runyan, Arthur J; Dave Airlie
>Subject: [PATCH] drm/i915: GEN7_MSG_CONTROL is ivb-only
>
>At least I couldn't find it in the Haswell Bspec any more and we've
>tried to test-boot a Haswell machine with num_pipes forced to 0 (i.e.
>hit the PCH_NOP path) and the unclaimed register logic complained.
>
>So restrict this dance to just ivb platforms.
>
>v2: Art pointed out that the bits simply moved on hsw+
>
>v3: Buy code terseneness with a notch of sublety as suggested by
>Chris.
>
>v4: Frob the right bit, spotted by Art.
>
>Cc: Chris Wilson <ch...@chris-wilson.co.uk>
>Cc: Arthur Ranyan <arthur.j.run...@intel.com>
>Cc: Dave Airlie <airl...@gmail.com>
>Signed-off-by: Daniel Vetter <daniel.vet...@ffwll.ch>
Reviewed-by: Art Runyan <arthur.j.run...@intel.com>
>---
> drivers/gpu/drm/i915/i915_gem.c | 12 +++++++++---
> drivers/gpu/drm/i915/i915_reg.h | 2 ++
> 2 files changed, 11 insertions(+), 3 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
>index 32636a470367..c57ecff4ea00 100644
>--- a/drivers/gpu/drm/i915/i915_gem.c
>+++ b/drivers/gpu/drm/i915/i915_gem.c
>@@ -4496,9 +4496,15 @@ i915_gem_init_hw(struct drm_device *dev)
> LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
>
> if (HAS_PCH_NOP(dev)) {
>- u32 temp = I915_READ(GEN7_MSG_CTL);
>- temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
>- I915_WRITE(GEN7_MSG_CTL, temp);
>+ if (IS_IVYBRIDGE(dev)) {
>+ u32 temp = I915_READ(GEN7_MSG_CTL);
>+ temp &= ~(WAIT_FOR_PCH_FLR_ACK |
>WAIT_FOR_PCH_RESET_ACK);
>+ I915_WRITE(GEN7_MSG_CTL, temp);
>+ } else if (INTEL_INFO(dev)->gen >= 7) {
>+ u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
>+ temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
>+ I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
>+ }
> }
>
> i915_gem_init_swizzling(dev);
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index 76126e0ae609..775fc26d53b8 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -4117,6 +4117,8 @@
> #define GEN7_MSG_CTL 0x45010
> #define WAIT_FOR_PCH_RESET_ACK (1<<1)
> #define WAIT_FOR_PCH_FLR_ACK (1<<0)
>+#define HSW_NDE_RSTWRN_OPT 0x46408
>+#define RESET_PCH_HANDSHAKE_ENABLE (1<<4)
>
> /* GEN7 chicken */
> #define GEN7_COMMON_SLICE_CHICKEN1 0x7010
>--
>1.8.5.2
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