On Thu, 27 Feb 2014 19:26:45 -0300
Paulo Zanoni <przan...@gmail.com> wrote:
> From: Paulo Zanoni <paulo.r.zan...@intel.com>
>
> It was just being used on debugfs and on a WARN inside
> hsw_set_power_well. But now that we PC8 is part of runtime PM and we
> get/put runtime PM when we get/put any power domain, we shouldn't need
> the WARN anymore.
>
> v2: - Rebase.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zan...@intel.com>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 1 -
> drivers/gpu/drm/i915/i915_drv.h | 2 --
> drivers/gpu/drm/i915/intel_display.c | 3 ---
> drivers/gpu/drm/i915/intel_pm.c | 3 ---
> 4 files changed, 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index ad6c209..93d6065 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2000,7 +2000,6 @@ static int i915_pc8_status(struct seq_file *m, void
> *unused)
> seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
> seq_printf(m, "IRQs disabled: %s\n",
> yesno(dev_priv->pc8.irqs_disabled));
> - seq_printf(m, "Enabled: %s\n", yesno(dev_priv->pc8.enabled));
> mutex_unlock(&dev_priv->pc8.lock);
>
> return 0;
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 8b66c14..16e344e 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1351,8 +1351,6 @@ struct ilk_wm_values {
> */
> struct i915_package_c8 {
> bool irqs_disabled;
> - /* Only true after the delayed work task actually enables it. */
> - bool enabled;
> struct mutex lock;
>
> struct {
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index d9ea9b89..271dd66 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6660,8 +6660,6 @@ void __hsw_do_enable_pc8(struct drm_i915_private
> *dev_priv)
>
> DRM_DEBUG_KMS("Enabling package C8+\n");
>
> - dev_priv->pc8.enabled = true;
> -
> if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
> val = I915_READ(SOUTH_DSPCLK_GATE_D);
> val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
> @@ -6697,7 +6695,6 @@ void __hsw_do_disable_pc8(struct drm_i915_private
> *dev_priv)
> mutex_lock(&dev_priv->rps.hw_lock);
> gen6_update_ring_freq(dev);
> mutex_unlock(&dev_priv->rps.hw_lock);
> - dev_priv->pc8.enabled = false;
> }
>
> #define for_each_power_domain(domain, mask) \
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 78f56e8..c85507a 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5278,8 +5278,6 @@ static void hsw_set_power_well(struct drm_device *dev,
> bool is_enabled, enable_requested;
> uint32_t tmp;
>
> - WARN_ON(dev_priv->pc8.enabled);
> -
> tmp = I915_READ(HSW_PWR_WELL_DRIVER);
> is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
> enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
> @@ -5773,7 +5771,6 @@ void intel_pm_setup(struct drm_device *dev)
>
> mutex_init(&dev_priv->pc8.lock);
> dev_priv->pc8.irqs_disabled = false;
> - dev_priv->pc8.enabled = false;
> INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
> intel_gen6_powersave_work);
> }
Reviewed-by: Jesse Barnes <jbar...@virtuousgeek.org>
--
Jesse Barnes, Intel Open Source Technology Center
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