[PATCH 5/6] drm/i915/psr: Allow setting I915_PSR_DEBUG_SU_REGION_ET_DISABLE via debugfs

[Jouni Högander]

Currently setting I915_PSR_DEBUG_SU_REGION_ET_DISABLE (0x20) via psr_debug
debugfs interface is not allowed. This patch allows it.

v3:
  - ensure psr is disabled/enabled if enable_psr2_su_region_et changes
  - remove extra space
v2: ensure that fastset is performed when the bit changes

Signed-off-by: Jouni Högander <jouni.hogan...@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c 
b/drivers/gpu/drm/i915/display/intel_psr.c
index 605ca6b6321d..16fa70c3ae45 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -2773,12 +2773,15 @@ void intel_psr_pre_plane_update(struct 
intel_atomic_state *state,
                 * - PSR disabled in new state
                 * - All planes will go inactive
                 * - Changing between PSR versions
+                * - Region Early Transport changing
                 * - Display WA #1136: skl, bxt
                 */
                needs_to_disable |= intel_crtc_needs_modeset(new_crtc_state);
                needs_to_disable |= !new_crtc_state->has_psr;
                needs_to_disable |= !new_crtc_state->active_planes;
                needs_to_disable |= new_crtc_state->has_sel_update != 
psr->sel_update_enabled;
+               needs_to_disable |= new_crtc_state->enable_psr2_su_region_et !=
+                       psr->su_region_et_enabled;
                needs_to_disable |= DISPLAY_VER(i915) < 11 &&
                        new_crtc_state->wm_level_disabled;
 
@@ -3014,10 +3017,12 @@ int intel_psr_debug_set(struct intel_dp *intel_dp, u64 
val)
 {
        struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
        const u32 mode = val & I915_PSR_DEBUG_MODE_MASK;
-       u32 old_mode;
+       const u32 disable_bits = val & I915_PSR_DEBUG_SU_REGION_ET_DISABLE;
+       u32 old_mode, old_disable_bits;
        int ret;
 
-       if (val & ~(I915_PSR_DEBUG_IRQ | I915_PSR_DEBUG_MODE_MASK) ||
+       if (val & ~(I915_PSR_DEBUG_IRQ | I915_PSR_DEBUG_SU_REGION_ET_DISABLE |
+                   I915_PSR_DEBUG_MODE_MASK) ||
            mode > I915_PSR_DEBUG_ENABLE_SEL_FETCH) {
                drm_dbg_kms(&dev_priv->drm, "Invalid debug mask %llx\n", val);
                return -EINVAL;
@@ -3028,6 +3033,8 @@ int intel_psr_debug_set(struct intel_dp *intel_dp, u64 
val)
                return ret;
 
        old_mode = intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK;
+       old_disable_bits = intel_dp->psr.debug &
+               I915_PSR_DEBUG_SU_REGION_ET_DISABLE;
        intel_dp->psr.debug = val;
 
        /*
@@ -3039,7 +3046,7 @@ int intel_psr_debug_set(struct intel_dp *intel_dp, u64 
val)
 
        mutex_unlock(&intel_dp->psr.lock);
 
-       if (old_mode != mode)
+       if (old_mode != mode || old_disable_bits != disable_bits)
                ret = intel_psr_fastset_force(dev_priv);
 
        return ret;
-- 
2.34.1