On Tue, 28 May 2024, Jani Nikula <jani.nik...@intel.com> wrote:
> The rawclk initialization is a bit out of place in
> intel_device_info_runtime_init(). Move it to intel_cdclk_init(), with a
> bit of refactoring on intel_read_rawclk().
Note: This also starts to initialize rawclk_frew for xe, which didn't
happen before. Apparently we didn't need it yet? Or the only user was
backlight max deduction?
BR,
Jani.
>
> Signed-off-by: Jani Nikula <jani.nik...@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 23 +++++++++++-----------
> drivers/gpu/drm/i915/display/intel_cdclk.h | 1 -
> drivers/gpu/drm/i915/intel_device_info.c | 4 ----
> 3 files changed, 11 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index c731c489c925..55c2dfe5422f 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -3218,6 +3218,8 @@ int intel_cdclk_state_set_joined_mbus(struct
> intel_atomic_state *state, bool joi
> return intel_atomic_lock_global_state(&cdclk_state->base);
> }
>
> +static void intel_rawclk_init(struct drm_i915_private *dev_priv);
> +
> int intel_cdclk_init(struct drm_i915_private *dev_priv)
> {
> struct intel_cdclk_state *cdclk_state;
> @@ -3229,6 +3231,8 @@ int intel_cdclk_init(struct drm_i915_private *dev_priv)
> intel_atomic_global_obj_init(dev_priv, &dev_priv->display.cdclk.obj,
> &cdclk_state->base, &intel_cdclk_funcs);
>
> + intel_rawclk_init(dev_priv);
> +
> return 0;
> }
>
> @@ -3545,16 +3549,13 @@ static int i9xx_hrawclk(struct drm_i915_private *i915)
> return DIV_ROUND_CLOSEST(i9xx_fsb_freq(i915), 4);
> }
>
> -/**
> - * intel_read_rawclk - Determine the current RAWCLK frequency
> - * @dev_priv: i915 device
> - *
> - * Determine the current RAWCLK frequency. RAWCLK is a fixed
> - * frequency clock so this needs to done only once.
> +/*
> + * Initialize the current RAWCLK frequency. RAWCLK is a fixed frequency
> clock so
> + * this needs to done only once.
> */
> -u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
> +static void intel_rawclk_init(struct drm_i915_private *dev_priv)
> {
> - u32 freq;
> + u32 freq = 0;
>
> if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTL)
> /*
> @@ -3573,11 +3574,9 @@ u32 intel_read_rawclk(struct drm_i915_private
> *dev_priv)
> freq = vlv_hrawclk(dev_priv);
> else if (DISPLAY_VER(dev_priv) >= 3)
> freq = i9xx_hrawclk(dev_priv);
> - else
> - /* no rawclk on other platforms, or no need to know it */
> - return 0;
>
> - return freq;
> + RUNTIME_INFO(dev_priv)->rawclk_freq = freq;
> + drm_dbg_kms(&dev_priv->drm, "rawclk rate: %d kHz\n", freq);
> }
>
> static int i915_cdclk_info_show(struct seq_file *m, void *unused)
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h
> b/drivers/gpu/drm/i915/display/intel_cdclk.h
> index cfdcdec07a4d..a3f950d5a366 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.h
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
> @@ -64,7 +64,6 @@ void intel_cdclk_uninit_hw(struct drm_i915_private *i915);
> void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
> void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
> void intel_update_cdclk(struct drm_i915_private *dev_priv);
> -u32 intel_read_rawclk(struct drm_i915_private *dev_priv);
> bool intel_cdclk_clock_changed(const struct intel_cdclk_config *a,
> const struct intel_cdclk_config *b);
> int intel_mdclk_cdclk_ratio(struct drm_i915_private *i915,
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> b/drivers/gpu/drm/i915/intel_device_info.c
> index 862f4b705227..cc7a8fb0a87d 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -370,10 +370,6 @@ void intel_device_info_runtime_init(struct
> drm_i915_private *dev_priv)
> "Disabling ppGTT for VT-d support\n");
> runtime->ppgtt_type = INTEL_PPGTT_NONE;
> }
> -
> - runtime->rawclk_freq = intel_read_rawclk(dev_priv);
> - drm_dbg(&dev_priv->drm, "rawclk rate: %d kHz\n", runtime->rawclk_freq);
> -
> }
>
> /*
--
Jani Nikula, Intel
