From: Ville Syrjälä <[email protected]> All the if statements in vlv_dsi_min_cdclk() check for INTEL_OUTPUT_DSI. Make life simpler by checking that just once at the start.
Signed-off-by: Ville Syrjälä <[email protected]> --- drivers/gpu/drm/i915/display/vlv_dsi.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c index 49a895589150..708639178e29 100644 --- a/drivers/gpu/drm/i915/display/vlv_dsi.c +++ b/drivers/gpu/drm/i915/display/vlv_dsi.c @@ -1763,26 +1763,26 @@ static void vlv_dphy_param_init(struct intel_dsi *intel_dsi) int vlv_dsi_min_cdclk(const struct intel_crtc_state *crtc_state) { struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); - int min_cdclk = 0; + + if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) + return 0; /* * On Valleyview some DSI panels lose (v|h)sync when the clock is lower * than 320000KHz. */ - if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) && - IS_VALLEYVIEW(dev_priv)) - min_cdclk = max(320000, min_cdclk); + if (IS_VALLEYVIEW(dev_priv)) + return 320000; /* * On Geminilake once the CDCLK gets as low as 79200 * picture gets unstable, despite that values are * correct for DSI PLL and DE PLL. */ - if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) && - IS_GEMINILAKE(dev_priv)) - min_cdclk = max(158400, min_cdclk); + if (IS_GEMINILAKE(dev_priv)) + return 158400; - return min_cdclk; + return 0; } typedef void (*vlv_dsi_dmi_quirk_func)(struct intel_dsi *intel_dsi); -- 2.45.2
