On Tue, 29 Oct 2024, Ville Syrjala <[email protected]> wrote: > From: Ville Syrjälä <[email protected]> > > Make the code a bit more self documenting by adding > HAS_DOUBLE_WIDE(). > > Signed-off-by: Ville Syrjälä <[email protected]>
Reviewed-by: Jani Nikula <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +- > drivers/gpu/drm/i915/display/intel_display.c | 4 ++-- > drivers/gpu/drm/i915/display/intel_display_device.h | 1 + > 3 files changed, 4 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c > b/drivers/gpu/drm/i915/display/intel_cdclk.c > index 96523526a2c3..6cef3ca3a069 100644 > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c > @@ -3462,7 +3462,7 @@ static int intel_compute_max_dotclk(struct > intel_display *display) > return max_cdclk_freq; > else if (IS_CHERRYVIEW(dev_priv)) > return max_cdclk_freq*95/100; > - else if (DISPLAY_VER(display) < 4) > + else if (HAS_DOUBLE_WIDE(display)) > return 2*max_cdclk_freq*90/100; > else > return max_cdclk_freq*90/100; > diff --git a/drivers/gpu/drm/i915/display/intel_display.c > b/drivers/gpu/drm/i915/display/intel_display.c > index 0e6d6c8354ef..9a5102224c59 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -2371,7 +2371,7 @@ static bool intel_crtc_supports_double_wide(const > struct intel_crtc *crtc) > const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > > /* GDG double wide on either pipe, otherwise pipe A only */ > - return DISPLAY_VER(dev_priv) < 4 && > + return HAS_DOUBLE_WIDE(dev_priv) && > (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); > } > > @@ -3207,7 +3207,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc > *crtc, > > intel_color_get_config(pipe_config); > > - if (DISPLAY_VER(dev_priv) < 4) > + if (HAS_DOUBLE_WIDE(dev_priv)) > pipe_config->double_wide = tmp & TRANSCONF_DOUBLE_WIDE; > > intel_get_transcoder_timings(crtc, pipe_config); > diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h > b/drivers/gpu/drm/i915/display/intel_display_device.h > index 410f8b33a8a1..ae7a35cf44ca 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_device.h > +++ b/drivers/gpu/drm/i915/display/intel_display_device.h > @@ -129,6 +129,7 @@ enum intel_display_subplatform { > #define HAS_DISPLAY(i915) (DISPLAY_RUNTIME_INFO(i915)->pipe_mask > != 0) > #define HAS_DMC(i915) > (DISPLAY_RUNTIME_INFO(i915)->has_dmc) > #define HAS_DOUBLE_BUFFERED_M_N(i915) (DISPLAY_VER(i915) >= 9 || > IS_BROADWELL(i915)) > +#define HAS_DOUBLE_WIDE(i915) (DISPLAY_VER(i915) < 4) > #define HAS_DP_MST(i915) (DISPLAY_INFO(i915)->has_dp_mst) > #define HAS_DP20(i915) (IS_DG2(i915) || > DISPLAY_VER(i915) >= 14) > #define HAS_DPT(i915) (DISPLAY_VER(i915) >= 13) -- Jani Nikula, Intel
