> -----Original Message----- > From: Intel-gfx <[email protected]> On Behalf Of Jouni > Högander > Sent: Monday, 17 March 2025 10.19 > To: [email protected]; [email protected] > Cc: Hogander, Jouni <[email protected]> > Subject: [PATCH v2 04/11] drm/i915/dmc: Add PIPEDMC_BLOCK_PKGC_SW > definitions > > We need PIPEDMC_BLOCK_PKGC_SW definitions to implement workaround for > underrun on idle PSR HW issue (Wa_16025596647). Add > PIPEDMC_BLOCK_PKGC_SW register definitions. > > Bspec: 71265 >
Reviewed-by: Mika Kahola <[email protected]> > Signed-off-by: Jouni Högander <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_dmc_regs.h | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_dmc_regs.h > b/drivers/gpu/drm/i915/display/intel_dmc_regs.h > index 2f1e3cb1a2477..e16ea3f16ed88 100644 > --- a/drivers/gpu/drm/i915/display/intel_dmc_regs.h > +++ b/drivers/gpu/drm/i915/display/intel_dmc_regs.h > @@ -27,6 +27,14 @@ > > _MTL_PIPEDMC_EVT_CTL_4_A, \ > > _MTL_PIPEDMC_EVT_CTL_4_B) > > +#define PIPEDMC_BLOCK_PKGC_SW_A 0x5f1d0 > +#define PIPEDMC_BLOCK_PKGC_SW_B 0x5F5d0 > +#define PIPEDMC_BLOCK_PKGC_SW(pipe) > _MMIO_PIPE(pipe, \ > + > PIPEDMC_BLOCK_PKGC_SW_A, \ > + > PIPEDMC_BLOCK_PKGC_SW_B) > +#define PIPEDMC_BLOCK_PKGC_SW_BLOCK_PKGC_ALWAYS > BIT(31) > +#define PIPEDMC_BLOCK_PKGC_SW_BLOCK_PKGC_UNTIL_NEXT_FRAMESTART > BIT(15) > + > #define _ADLP_PIPEDMC_REG_MMIO_BASE_A 0x5f000 > #define _TGL_PIPEDMC_REG_MMIO_BASE_A 0x92000 > > -- > 2.43.0
