> -----Original Message----- > From: Intel-xe <[email protected]> On Behalf Of Jouni > Högander > Sent: Monday, 17 March 2025 10.19 > To: [email protected]; [email protected] > Cc: Hogander, Jouni <[email protected]> > Subject: [PATCH v2 08/11] drm/i915/psr: Add interface to notify PSR of vblank > enable/disable > > To implement Wa_16025596647 we need to get notification of vblank interrupt > enable/disable. Add new interface to PSR code for this notification. >
Reviewed-by: Mika Kahola <[email protected]> > Signed-off-by: Jouni Högander <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_psr.c | 40 ++++++++++++++++++++++++ > drivers/gpu/drm/i915/display/intel_psr.h | 2 ++ > 2 files changed, 42 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > b/drivers/gpu/drm/i915/display/intel_psr.c > index baf6a7110a555..afb9faed7784b 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -3820,6 +3820,46 @@ void intel_psr_notify_pipe_change(struct > intel_atomic_state *state, > } > } > > +/** > + * intel_psr_notify_vblank_enable_disable - Notify PSR about > +enable/disable of vblank > + * @display: intel display struct > + * @enable: enable/disable > + * > + * This is targeted for underrun on idle PSR HW bug (Wa_16025596647) to > +apply > + * remove the workaround when vblank is getting enabled/disabled */ > +void intel_psr_notify_vblank_enable_disable(struct intel_display *display, > + bool enable) > +{ > + struct intel_encoder *encoder; > + > + for_each_intel_encoder_with_psr(display->drm, encoder) { > + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); > + > + mutex_lock(&intel_dp->psr.lock); > + if (intel_dp->psr.panel_replay_enabled) { > + mutex_unlock(&intel_dp->psr.lock); > + break; > + } > + > + if (intel_dp->psr.enabled) > + > intel_psr_apply_underrun_on_idle_wa_locked(intel_dp); > + > + mutex_unlock(&intel_dp->psr.lock); > + return; > + } > + > + /* > + * NOTE: intel_display_power_set_target_dc_state is used > + * only by PSR * code for DC3CO handling. DC3CO target > + * state is currently disabled in * PSR code. If DC3CO > + * is taken into use we need take that into account here > + * as well. > + */ > + intel_display_power_set_target_dc_state(display, enable ? > DC_STATE_DISABLE : > + DC_STATE_EN_UPTO_DC6); > +} > + > static void > psr_source_status(struct intel_dp *intel_dp, struct seq_file *m) { diff > --git > a/drivers/gpu/drm/i915/display/intel_psr.h > b/drivers/gpu/drm/i915/display/intel_psr.h > index bfe368239bc27..a914b7ee3756a 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.h > +++ b/drivers/gpu/drm/i915/display/intel_psr.h > @@ -64,6 +64,8 @@ void intel_psr_notify_pipe_change(struct > intel_atomic_state *state, > struct intel_crtc *crtc, bool enable); void > intel_psr_notify_dc5_dc6(struct intel_display *display); void > intel_psr_dc5_dc6_wa_init(struct intel_display *display); > +void intel_psr_notify_vblank_enable_disable(struct intel_display *display, > + bool enable); > bool intel_psr_link_ok(struct intel_dp *intel_dp); > > void intel_psr_lock(const struct intel_crtc_state *crtc_state); > -- > 2.43.0
