On Fri, Oct 24, 2025 at 07:09:19PM +0530, Nautiyal, Ankit K wrote: > > On 10/21/2025 12:20 AM, Ville Syrjala wrote: > > From: Ville Syrjälä <[email protected]> > > > > EMP_AS_SDL_TL replaces the TRANS_VRR_VSUNC for the purposes of > > Nitpick: typo TRANS_VRR_VSYNC. > > > > setting the AS SDP transmission line. Move the EMP_AS_SDL_TL into > > intel_vrr_set_transcoder_timings() since that's where we write > > TRANS_VRR_VSYNC as well. > > > Not related to this change, but perhaps at some point we might need to > come with a policy if there are more SDPs that have configurable > Transmission lines and DB point. > > We have VS_SDP_TL for PTL (we do not use VS_SDP currently), and some > more for NVL.
Yeah, I think this actually the wrong place to program this as it also affects infoframes on HDMI. Probably all these should be in the infoframe code somewhere. > > > > > Signed-off-by: Ville Syrjälä <[email protected]> > > Reviewed-by: Ankit Nautiyal <[email protected]> > > > > --- > > drivers/gpu/drm/i915/display/intel_vrr.c | 35 ++++++++---------------- > > 1 file changed, 12 insertions(+), 23 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c > > b/drivers/gpu/drm/i915/display/intel_vrr.c > > index 6e8f8e673312..562a5feadaab 100644 > > --- a/drivers/gpu/drm/i915/display/intel_vrr.c > > +++ b/drivers/gpu/drm/i915/display/intel_vrr.c > > @@ -571,6 +571,18 @@ void intel_vrr_set_transcoder_timings(const struct > > intel_crtc_state *crtc_state) > > TRANS_VRR_VSYNC(display, cpu_transcoder), > > VRR_VSYNC_END(crtc_state->vrr.vsync_end) | > > VRR_VSYNC_START(crtc_state->vrr.vsync_start)); > > + > > + /* > > + * For BMG and LNL+ onwards the EMP_AS_SDP_TL is used for programming > > + * double buffering point and transmission line for VRR packets for > > + * HDMI2.1/DP/eDP/DP->HDMI2.1 PCON. > > + * Since currently we support VRR only for DP/eDP, so this is programmed > > + * to for Adaptive Sync SDP to Vsync start. > > + */ > > + if (DISPLAY_VERx100(display) == 1401 || DISPLAY_VER(display) >= 20) > > + intel_de_write(display, > > + EMP_AS_SDP_TL(display, cpu_transcoder), > > + EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start)); > > } > > > > void intel_vrr_send_push(struct intel_dsb *dsb, > > @@ -649,25 +661,6 @@ bool intel_vrr_always_use_vrr_tg(struct intel_display > > *display) > > return false; > > } > > > > -static > > -void intel_vrr_set_db_point_and_transmission_line(const struct > > intel_crtc_state *crtc_state) > > -{ > > - struct intel_display *display = to_intel_display(crtc_state); > > - enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; > > - > > - /* > > - * For BMG and LNL+ onwards the EMP_AS_SDP_TL is used for programming > > - * double buffering point and transmission line for VRR packets for > > - * HDMI2.1/DP/eDP/DP->HDMI2.1 PCON. > > - * Since currently we support VRR only for DP/eDP, so this is programmed > > - * to for Adaptive Sync SDP to Vsync start. > > - */ > > - if (DISPLAY_VERx100(display) == 1401 || DISPLAY_VER(display) >= 20) > > - intel_de_write(display, > > - EMP_AS_SDP_TL(display, cpu_transcoder), > > - EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start)); > > -} > > - > > static int intel_vrr_hw_vmin(const struct intel_crtc_state *crtc_state) > > { > > struct intel_display *display = to_intel_display(crtc_state); > > @@ -710,8 +703,6 @@ void intel_vrr_enable(const struct intel_crtc_state > > *crtc_state) > > intel_vrr_set_vrr_timings(crtc_state); > > > > if (!intel_vrr_always_use_vrr_tg(display)) { > > - intel_vrr_set_db_point_and_transmission_line(crtc_state); > > - > > intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), > > TRANS_PUSH_EN); > > > > @@ -773,8 +764,6 @@ void intel_vrr_transcoder_enable(const struct > > intel_crtc_state *crtc_state) > > intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), > > TRANS_PUSH_EN); > > > > - intel_vrr_set_db_point_and_transmission_line(crtc_state); > > - > > intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), > > VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state)); > > } -- Ville Syrjälä Intel
