This is v2 of [1], with the following changes - Add support for eDP on C20 phy pll on PantherLake.
- As required by the above point use the non_tc_phy instead of c10phy term for the PLL hooks computing the state for, getting/putting etc. the PLLs of the non TypeC ports/outputs (on port A and B). Use the tc_phy instead of the c20phy term for the PLLs of all the other TypeC ports/outputs (port TC1-4).Support for eDP on C20 phy pll on PantherLake. [1] https://lore.kernel.org/intel-xe/[email protected]/ Imre Deak (15): drm/i915/display: Factor out C10 msgbus access start/end helpers drm/i915/display: Sanitize setting the Cx0 PLL use_c10 flag drm/i915/display: Sanitize calculating C20 PLL state from tables drm/i915/display: Track the C20 PHY VDR state in the PLL state drm/i915/display: Move definition of Cx0 PHY functions earlier drm/i915/display: Add macro to get DDI port width from a register value drm/i915/display: Track the Cx0 PHY enabled lane count in the PLL state drm/i915/display: Sanitize C10 PHY PLL SSC register setup drm/i915/display: Read out the Cx0 PHY SSC enabled state drm/i915/display: Determine Cx0 PLL DP mode from PLL state drm/i915/display: Determine Cx0 PLL port clock from PLL state drm/i915/display: Zero Cx0 PLL state before compute and HW readout drm/i915/display: Print additional Cx0 PLL HW state drm/i915/display: PLL verify debug state print drm/i915/display: Add Thunderbolt support Mika Kahola (17): drm/i915/display: Rename TBT functions to be ICL specific drm/i915/display: Remove state verification drm/i915/display: PLL information for MTL+ drm/i915/display: Update C10/C20 state calculation drm/i915/display: Compute plls for MTL+ platform drm/i915/display: MTL+ .get_dplls drm/i915/display: MTL+ .put_dplls drm/i915/display: Add .update_active_dpll drm/i915/display: Add .update_dpll_ref_clks drm/i915/display: Add .dump_hw_state drm/i915/display: Add .compare_hw_state drm/i915/display: Add .get_hw_state to MTL+ platforms drm/i915/display: Add .get_freq to MTL+ platforms drm/i915/display: Add .crtc_get_dpll hook drm/i915/display: Add .enable_clock on DDI for MTL+ platforms drm/i915/display: Get configuration for C10 and C20 drm/i915/display: Enable dpll framework for MTL+ drivers/gpu/drm/i915/display/intel_cx0_phy.c | 896 ++++++++++-------- drivers/gpu/drm/i915/display/intel_cx0_phy.h | 25 +- drivers/gpu/drm/i915/display/intel_ddi.c | 81 +- drivers/gpu/drm/i915/display/intel_display.c | 32 - .../gpu/drm/i915/display/intel_display_regs.h | 7 +- drivers/gpu/drm/i915/display/intel_dpll.c | 24 +- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 314 +++++- drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 7 + .../drm/i915/display/intel_modeset_verify.c | 1 - 9 files changed, 893 insertions(+), 494 deletions(-) -- 2.34.1
