> -----Original Message----- > From: Sousa, Gustavo <[email protected]> > Sent: Monday, November 3, 2025 10:48 PM > To: [email protected]; [email protected] > Cc: Nautiyal, Ankit K <[email protected]>; Bhadane, Dnyaneshwar > <[email protected]>; Sousa, Gustavo > <[email protected]>; Hogander, Jouni <[email protected]>; > Heikkila, Juha-pekka <[email protected]>; Coelho, Luciano > <[email protected]>; De Marchi, Lucas <[email protected]>; > Atwood, Matthew S <[email protected]>; Roper, Matthew D > <[email protected]>; Vodapalli, Ravi Kumar > <[email protected]>; Chauhan, Shekhar > <[email protected]>; Govindapillai, Vinod > <[email protected]>; Kandpal, Suraj <[email protected]> > Subject: [PATCH v3 27/29] drm/i915/display: Use platform check in > HAS_LT_PHY() > > NVL uses the Lake Tahoe PHY for display output and the driver recently added > the macro HAS_LT_PHY() to allow selecting code paths specific for that type of > PHY. > > While NVL uses Xe3p_LPD as display IP, the type of PHY is actually defined at > the SoC level, so use a platform check instead of display version. > > Bspec: 74199 > Cc: Suraj Kandpal <[email protected]> > Cc: Matt Roper <[email protected]> > Signed-off-by: Gustavo Sousa <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_lt_phy.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h > b/drivers/gpu/drm/i915/display/intel_lt_phy.h > index a538d4c69210..034c20c66baf 100644 > --- a/drivers/gpu/drm/i915/display/intel_lt_phy.h > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h > @@ -39,6 +39,6 @@ void intel_xe3plpd_pll_enable(struct intel_encoder > *encoder, > const struct intel_crtc_state *crtc_state); void > intel_xe3plpd_pll_disable(struct intel_encoder *encoder); > > -#define HAS_LT_PHY(display) (DISPLAY_VER(display) >= 35) > +#define HAS_LT_PHY(display) ((display)->platform.novalake)
LGTM, Reviewed-by: Dnyaneshwar Bhadane <[email protected]> Dnyaneshwar > > #endif /* __INTEL_LT_PHY_H__ */ > > -- > 2.51.0
