On Tue, Nov 04, 2025 at 04:48:40PM +0530, Nitin Gote wrote:
The register at offset 0xfd0 was incorrectly named MCFG_MCR_SELECTOR.
According to the hardware specification (Bspec), this register is
actually called STEER_SEMAPHORE.
Rename the register definition and update its usage to
match the official hardware documentation.
No functional changes.
Bspec: 67113
I'm looking at this since you asked me about a similar patch I merged in
xe. In xe it's a little bit different since we start official support at
Xe2 platforms.
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 7421ed18d8d1..2282c1f16f44 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -62,8 +62,7 @@
#define GMD_ID_GRAPHICS _MMIO(0xd8c)
#define GMD_ID_MEDIA _MMIO(MTL_MEDIA_GSI_BASE +
0xd8c)
-#define MCFG_MCR_SELECTOR _MMIO(0xfd0)
-#define MTL_STEER_SEMAPHORE _MMIO(0xfd0)
+#define STEER_SEMAPHORE _MMIO(0xfd0)
bspec 52127... before MTL this register was called MCRPKT_CTRL_MCFG
prefixing with the platform where it changed, for clarity, follows what
is done in i915.
I think calling it STEER_SEMAPHORE for all platforms would make it
clearer, but I'm not sure it's needed/desired. I will leave it to
maintainers to decide.
Lucas De Marchi
#define MTL_MCR_SELECTOR _MMIO(0xfd4)
#define SF_MCR_SELECTOR _MMIO(0xfd8)
#define GEN8_MCR_SELECTOR _MMIO(0xfdc)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index ece88c612e27..594730f221b8 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1405,7 +1405,7 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list
*wal)
* we'll just steer to a hardcoded "2" since that value will work
* everywhere.
*/
- __set_mcr_steering(wal, MCFG_MCR_SELECTOR, 0, 2);
+ __set_mcr_steering(wal, STEER_SEMAPHORE, 0, 2);
__set_mcr_steering(wal, SF_MCR_SELECTOR, 0, 2);
/*
--
2.25.1
