> Subject: [PATCH 4/5] drm/i915/cx0: Read out power-down state of both TXs in > PHY lane 0 > > If the number of used lanes is 1 or 2 then the power-down state of both TX > lanes in PHY lane 0 should be read out. If 1 lane is used only 1 TX lane will > be > checked, make sure both TXs are checked in this case. > > Cc: Mika Kahola <[email protected]> > Cc: Suraj Kandpal <[email protected]> > Fixes: 230d4c748113 ("drm/i915/cx0: Track the Cx0 PHY enabled lane count in > the PLL state") > Signed-off-by: Imre Deak <[email protected]>
LGTM, Reviewed-by: Suraj Kandpal <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c > index 96ab7f3b5539c..0d524735dcf95 100644 > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c > @@ -2209,7 +2209,7 @@ static int readout_enabled_lane_count(struct > intel_encoder *encoder) > */ > max_tx_lane_count = DDI_PORT_WIDTH_GET(intel_de_read(display, > DDI_BUF_CTL(encoder->port))); > if (!drm_WARN_ON(display->drm, max_tx_lane_count == 0)) > - max_tx_lane_count = > roundup_pow_of_two(max_tx_lane_count); > + max_tx_lane_count = round_up(max_tx_lane_count, 2); > > for (tx_lane = 0; tx_lane < max_tx_lane_count; tx_lane++) { > u8 phy_lane_mask = tx_lane < 2 ? INTEL_CX0_LANE0 : > INTEL_CX0_LANE1; > -- > 2.49.1
