> Subject: [PATCH 5/5] drm/i915/cx0: Read out power-down state of both PHY > lanes for reversed lanes > > For a port used with lane reversal enabled the first two TX lanes will be > enabled > in PHY lane#1 instead of PHY lane#0. At the moment the HW readout will read > out the power-down state for these two TX lanes from PHY lane#0 incorrectly. > The display HW lane reversal feature (vs. the similar TCSS lane swap) is only > used for TypeC legacy mode and for non-TypeC PHYs. Since in both of these > cases the display owns both PHY lanes, both of these PHY lanes' state can be > read out. Do that to fix cases when lane reversal is used with 1 or 2 active > TX > lanes. > > While at it add an assert to the PLL enable function about the above > assumption on when lane reversal can be used. > > Cc: Mika Kahola <[email protected]> > Cc: Suraj Kandpal <[email protected]> > Fixes: 230d4c748113 ("drm/i915/cx0: Track the Cx0 PHY enabled lane count in > the PLL state") > Signed-off-by: Imre Deak <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 24 ++++++++++++++++++-- > 1 file changed, 22 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c > index 0d524735dcf95..27be2a490297f 100644 > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c > @@ -2197,17 +2197,30 @@ static int readout_enabled_lane_count(struct > intel_encoder *encoder) { > struct intel_display *display = to_intel_display(encoder); > u8 enabled_tx_lane_count = 0; > - int max_tx_lane_count; > + int max_tx_lane_count = 4; > + bool lane_reversal; > int tx_lane; > > + lane_reversal = intel_de_read(display, XELPDP_PORT_BUF_CTL1(display, > encoder->port)) & > + XELPDP_PORT_REVERSAL; > +
Can't we just do struct intel_digital_port *dig_port = enc_to_dig_port(encoder); bool lane_reversal = dig_port->lane_reversal; or are there limitations with that now? Regards. Suraj Kandpal > /* > * TODO: also check inactive TX lanes in all PHY lanes owned by the > * display. For now checking only those PHY lane(s) which are owned > * based on the active TX lane count (i.e. > * 1,2 active TX lanes -> PHY lane#0 > * 3,4 active TX lanes -> PHY lane#0 and PHY lane#1). > + * > + * In case of lane reversal for 1, 2 active TX lanes, only PHY > + * lane#1 is used. This is only possible in TypeC legacy mode or if > + * the port is connected to a non-TC PHY. In both of these cases both > + * PHY lane#0 and #1 are owned by display, so check all 4 TX lanes in > + * both PHY lanes in those cases. > */ > - max_tx_lane_count = DDI_PORT_WIDTH_GET(intel_de_read(display, > DDI_BUF_CTL(encoder->port))); > + if (!lane_reversal) > + max_tx_lane_count = > DDI_PORT_WIDTH_GET(intel_de_read(display, > + > DDI_BUF_CTL(encoder->port))); > + > if (!drm_WARN_ON(display->drm, max_tx_lane_count == 0)) > max_tx_lane_count = round_up(max_tx_lane_count, 2); > > @@ -3214,6 +3227,13 @@ static void intel_cx0pll_enable(struct intel_encoder > *encoder, > INTEL_CX0_LANE0; > intel_wakeref_t wakeref = intel_cx0_phy_transaction_begin(encoder); > > + /* > + * Lane reversal is never used in DP-alt mode, in that case the > + * corresponding lane swapping (based on the TypeC cable flip state > + * for instance) is handled automatically by the HW via a TCSS mux. > + */ > + drm_WARN_ON(display->drm, lane_reversal && > +intel_tc_port_in_dp_alt_mode(dig_port)); > + > /* > * 1. Program PORT_CLOCK_CTL REGISTER to configure > * clock muxes, gating and SSC > -- > 2.49.1
