On Thu, 2025-11-27 at 19:50 +0200, Imre Deak wrote: > By now all the places are updated to track the DSC slice > configuration > in intel_crtc_state::dsc.slice_config, so calculate the slices-per- > line > value using that config, instead of using > intel_crtc_state::dsc.slice_count caching the same value and remove > the cached slice_count. > > Signed-off-by: Imre Deak <[email protected]>
Reviewed-by: Jouni Högander <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_bios.c | 6 ++---- > drivers/gpu/drm/i915/display/intel_display_types.h | 1 - > drivers/gpu/drm/i915/display/intel_dp.c | 11 +++++------ > drivers/gpu/drm/i915/display/intel_vdsc.c | 7 ++++--- > 4 files changed, 11 insertions(+), 14 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_bios.c > b/drivers/gpu/drm/i915/display/intel_bios.c > index 479c5f0158800..698e569a48e61 100644 > --- a/drivers/gpu/drm/i915/display/intel_bios.c > +++ b/drivers/gpu/drm/i915/display/intel_bios.c > @@ -3538,14 +3538,12 @@ static void fill_dsc(struct intel_crtc_state > *crtc_state, > crtc_state->dsc.slice_config.slices_per_stream = 1; > } > > - crtc_state->dsc.slice_count = > intel_dsc_line_slice_count(&crtc_state->dsc.slice_config); > - > if (crtc_state->hw.adjusted_mode.crtc_hdisplay % > - crtc_state->dsc.slice_count != 0) > + intel_dsc_line_slice_count(&crtc_state- > >dsc.slice_config) != 0) > drm_dbg_kms(display->drm, > "VBT: DSC hdisplay %d not divisible by > slice count %d\n", > crtc_state- > >hw.adjusted_mode.crtc_hdisplay, > - crtc_state->dsc.slice_count); > + intel_dsc_line_slice_count(&crtc_state- > >dsc.slice_config)); > > /* > * The VBT rc_buffer_block_size and rc_buffer_size > definitions > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h > b/drivers/gpu/drm/i915/display/intel_display_types.h > index 574fc7ff33c97..0f56be61f081b 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > @@ -1312,7 +1312,6 @@ struct intel_crtc_state { > } slice_config; > /* Compressed Bpp in U6.4 format (first 4 bits for > fractional part) */ > u16 compressed_bpp_x16; > - u8 slice_count; > struct drm_dsc_config config; > } dsc; > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > b/drivers/gpu/drm/i915/display/intel_dp.c > index d17afc18fcfa7..126048c5233c4 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -2031,12 +2031,14 @@ static int dsc_compute_link_config(struct > intel_dp *intel_dp, > } else { > unsigned long bw_overhead_flags = > pipe_config->fec_enable ? > DRM_DP_BW_OVERHEAD_FEC : 0; > + int line_slice_count = > + intel_dsc_line_slice_count(& > pipe_config->dsc.slice_config); > > if > (!is_bw_sufficient_for_dsc_config(intel_dp, > > link_rate, lane_count, > > adjusted_mode->crtc_clock, > > adjusted_mode->hdisplay, > - > pipe_config->dsc.slice_count, > + > line_slice_count, > > dsc_bpp_x16, > > bw_overhead_flags)) > continue; > @@ -2427,11 +2429,8 @@ int intel_dp_dsc_compute_config(struct > intel_dp *intel_dp, > pipe_config->dsc.slice_config.pipes_per_line / > pipe_config->dsc.slice_config.streams_per_pipe; > > - pipe_config->dsc.slice_count = > - intel_dsc_line_slice_count(&pipe_config- > >dsc.slice_config); > - > drm_WARN_ON(display->drm, > - pipe_config->dsc.slice_count != > slices_per_line); > + intel_dsc_line_slice_count(&pipe_config- > >dsc.slice_config) != slices_per_line); > > ret = intel_dp_dsc_compute_params(connector, pipe_config); > if (ret < 0) { > @@ -2449,7 +2448,7 @@ int intel_dp_dsc_compute_config(struct intel_dp > *intel_dp, > "Compressed Bpp = " FXP_Q4_FMT " Slice Count = > %d\n", > pipe_config->pipe_bpp, > FXP_Q4_ARGS(pipe_config- > >dsc.compressed_bpp_x16), > - pipe_config->dsc.slice_count); > + intel_dsc_line_slice_count(&pipe_config- > >dsc.slice_config)); > > return 0; > } > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c > b/drivers/gpu/drm/i915/display/intel_vdsc.c > index 2b27671f97b32..190ce567bc7fa 100644 > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c > @@ -283,8 +283,9 @@ int intel_dsc_compute_params(struct > intel_crtc_state *pipe_config) > int ret; > > vdsc_cfg->pic_width = pipe_config- > >hw.adjusted_mode.crtc_hdisplay; > - vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width, > - pipe_config- > >dsc.slice_count); > + vdsc_cfg->slice_width = > + DIV_ROUND_UP(vdsc_cfg->pic_width, > + > intel_dsc_line_slice_count(&pipe_config->dsc.slice_config)); > > err = intel_dsc_slice_dimensions_valid(pipe_config, > vdsc_cfg); > > @@ -1042,7 +1043,7 @@ static void intel_vdsc_dump_state(struct > drm_printer *p, int indent, > drm_printf_indent(p, indent, > "dsc-dss: compressed-bpp:" FXP_Q4_FMT ", > slice-count: %d, num_streams: %d\n", > FXP_Q4_ARGS(crtc_state- > >dsc.compressed_bpp_x16), > - crtc_state->dsc.slice_count, > + intel_dsc_line_slice_count(&crtc_state- > >dsc.slice_config), > crtc_state- > >dsc.slice_config.streams_per_pipe); > } >
