On Thu, 2025-11-27 at 19:50 +0200, Imre Deak wrote: > Simplify the slice config loop in intel_dp_dsc_get_slice_count(), > using > the loop iterator as the slices-per-pipe value directly, instead of > looking up the same value from an array. > > While at it move the code comment about the slice configuration > closer > to where the configuration is determined and clarify it a bit. > > Signed-off-by: Imre Deak <[email protected]>
Reviewed-by: Jouni Högander <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_dp.c | 33 ++++++++++------------- > -- > 1 file changed, 13 insertions(+), 20 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > b/drivers/gpu/drm/i915/display/intel_dp.c > index 650b339fd73bc..a4ff1ffc8f7d4 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -107,20 +107,6 @@ > /* Constants for DP DSC configurations */ > static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15}; > > -/* > - * With Single pipe configuration, HW is capable of supporting > maximum of: > - * 2 slices per line for ICL, BMG > - * 4 slices per line for other platforms. > - * For now consider a max of 2 slices per line, which works for all > platforms. > - * With this we can have max of 4 DSC Slices per pipe. > - * > - * For higher resolutions where 12 slice support is required with > - * ultrajoiner, only then each pipe can support 3 slices. > - * > - * #TODO Split this better to use 4 slices/dsc engine where > supported. > - */ > -static const u8 valid_dsc_slicecount[] = {1, 2, 3, 4}; > - > /** > * intel_dp_is_edp - is the given port attached to an eDP panel > (either CPU or PCH) > * @intel_dp: DP struct > @@ -1032,17 +1018,24 @@ u8 intel_dp_dsc_get_slice_count(const struct > intel_connector *connector, > intel_dp_dsc_min_slice_count(connector, mode_clock, > mode_hdisplay); > u32 sink_slice_count_mask = > drm_dp_dsc_sink_slice_count_mask(connector- > >dp.dsc_dpcd, false); > - int i; > + int slices_per_pipe; > > - /* Find the closest match to the valid slice count values */ > - for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) { > - int slices_per_line = valid_dsc_slicecount[i] * > num_joined_pipes; > + /* > + * Find the closest match to the valid slice count values > + * > + * Max HW DSC-per-pipe x slice-per-DSC (= slice-per-pipe) > capability: > + * ICL: 2x2 > + * BMG: 2x2, or for ultrajoined 4 pipes: 3x1 > + * TGL+: 2x4 (TODO: Add support for this) > + */ > + for (slices_per_pipe = 1; slices_per_pipe <= 4; > slices_per_pipe++) { > + int slices_per_line = slices_per_pipe * > num_joined_pipes; > > /* > * 3 DSC Slices per pipe need 3 DSC engines, which > is supported only > * with Ultrajoiner only for some platforms. > */ > - if (valid_dsc_slicecount[i] == 3 && > + if (slices_per_pipe == 3 && > (!HAS_DSC_3ENGINES(display) || num_joined_pipes > != 4)) > continue; > > @@ -1055,7 +1048,7 @@ u8 intel_dp_dsc_get_slice_count(const struct > intel_connector *connector, > * So there should be at least 2 dsc slices per > pipe, > * whenever bigjoiner is enabled. > */ > - if (num_joined_pipes > 1 && valid_dsc_slicecount[i] > < 2) > + if (num_joined_pipes > 1 && slices_per_pipe < 2) > continue; > > if (mode_hdisplay % slices_per_line)
