> Subject: [PATCH v2 13/15] drm/i915/cx0: Drop C20 25.175 MHz rate > > Drop C20 25.175 MHz pll table as with these pll dividers the port clock will > be > incorrectly calculated to 25.2 MHz. For 25.175 MHz rate the PLl dividers are > calculated algorithmically making pll table for this rate redundant.
* PLL Other than that LGTM, Reviewed-by: Suraj Kandpal <[email protected]> > > Signed-off-by: Mika Kahola <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 26 -------------------- > 1 file changed, 26 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c > index a8c37a14d427..5d0bca0f75b0 100644 > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c > @@ -1797,31 +1797,6 @@ static const struct intel_cx0pll_params > mtl_c10_hdmi_tables[] = { > {} > }; > > -static const struct intel_c20pll_state mtl_c20_hdmi_25_175 = { > - .clock = 25175, > - .tx = { 0xbe88, /* tx cfg0 */ > - 0x9800, /* tx cfg1 */ > - 0x0000, /* tx cfg2 */ > - }, > - .cmn = { 0x0500, /* cmn cfg0*/ > - 0x0005, /* cmn cfg1 */ > - 0x0000, /* cmn cfg2 */ > - 0x0000, /* cmn cfg3 */ > - }, > - .mpllb = { 0xa0d2, /* mpllb cfg0 */ > - 0x7d80, /* mpllb cfg1 */ > - 0x0906, /* mpllb cfg2 */ > - 0xbe40, /* mpllb cfg3 */ > - 0x0000, /* mpllb cfg4 */ > - 0x0000, /* mpllb cfg5 */ > - 0x0200, /* mpllb cfg6 */ > - 0x0001, /* mpllb cfg7 */ > - 0x0000, /* mpllb cfg8 */ > - 0x0000, /* mpllb cfg9 */ > - 0x0001, /* mpllb cfg10 */ > - }, > -}; > - > static const struct intel_c20pll_state mtl_c20_hdmi_27_0 = { > .clock = 27000, > .tx = { 0xbe88, /* tx cfg0 */ > @@ -2048,7 +2023,6 @@ static const struct intel_c20pll_state > mtl_c20_hdmi_1200 = { }; > > static const struct intel_cx0pll_params mtl_c20_hdmi_tables[] = { > - C20PLL_HDMI_PARAMS(25175, mtl_c20_hdmi_25_175), > C20PLL_HDMI_PARAMS(27000, mtl_c20_hdmi_27_0), > C20PLL_HDMI_PARAMS(74250, mtl_c20_hdmi_74_25), > C20PLL_HDMI_PARAMS(148500, mtl_c20_hdmi_148_5), > -- > 2.34.1
