Re: [PATCH 2/9] drm/i915/display: Replace DC_STATE_EN_DC3CO with DC_STATE_EN_UPTO_DC3CO

[Dibin Moolakadan Subrahmanian]

On 05-01-2026 18:15, Jani Nikula wrote:

On Tue, 09 Dec 2025, Dibin Moolakadan 
Subrahmanian<dibin.moolakadan.subrahman...@intel.com> wrote:

DC3CO no longer uses a standalone enable bit but part of existing
UPTO_DC* enable bits.

"no longer" for register contents absolutely requires references to the
platforms.

I will add platform details here.

Regards,
Dibin

Signed-off-by: Dibin Moolakadan 
Subrahmanian<dibin.moolakadan.subrahman...@intel.com>
---
  drivers/gpu/drm/i915/display/intel_display_power.c      | 6 +++---
  drivers/gpu/drm/i915/display/intel_display_power_well.c | 4 ++--
  drivers/gpu/drm/i915/display/intel_display_regs.h       | 2 +-
  drivers/gpu/drm/i915/display/intel_dmc_wl.c             | 2 +-
  4 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c 
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 9f323c39d798..0961b194554c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -267,7 +267,7 @@ sanitize_target_dc_state(struct intel_display *display,
        static const u32 states[] = {
                DC_STATE_EN_UPTO_DC6,
                DC_STATE_EN_UPTO_DC5,
-               DC_STATE_EN_DC3CO,
+               DC_STATE_EN_UPTO_DC3CO,
                DC_STATE_DISABLE,
        };
        int i;
@@ -999,10 +999,10 @@ static u32 get_allowed_dc_mask(struct intel_display 
*display, int enable_dc)

switch (requested_dc) {

        case 4:
-               mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6;
+               mask |= DC_STATE_EN_UPTO_DC3CO | DC_STATE_EN_UPTO_DC6;
                break;
        case 3:
-               mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC5;
+               mask |= DC_STATE_EN_UPTO_DC3CO | DC_STATE_EN_UPTO_DC5;
                break;
        case 2:
                mask |= DC_STATE_EN_UPTO_DC6;
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c 
b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 2dce622eb5d8..6f62a4420f6e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -727,7 +727,7 @@ static u32 gen9_dc_mask(struct intel_display *display)
        mask = DC_STATE_EN_UPTO_DC5;

if (DISPLAY_VER(display) >= 12)

-               mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6
+               mask |= DC_STATE_EN_UPTO_DC3CO | DC_STATE_EN_UPTO_DC6
                                          | DC_STATE_EN_DC9;
        else if (DISPLAY_VER(display) == 11)
                mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9;
@@ -977,7 +977,7 @@ static void bxt_verify_dpio_phy_power_wells(struct 
intel_display *display)
  static bool gen9_dc_off_power_well_enabled(struct intel_display *display,
                                           struct i915_power_well *power_well)
  {
-       return ((intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 
&&
+       return ((intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_UPTO_DC3CO) == 0 
&&
                (intel_de_read(display, DC_STATE_EN) & 
DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0);
  }

diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h

index 9e0d853f4b61..7e620e22718b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -2819,13 +2819,13 @@ enum skl_power_gate {
  /* GEN9 DC */
  #define DC_STATE_EN                   _MMIO(0x45504)
  #define  DC_STATE_DISABLE             0
-#define  DC_STATE_EN_DC3CO             REG_BIT(30)
  #define  DC_STATE_DC3CO_STATUS                REG_BIT(29)
  #define  HOLD_PHY_CLKREQ_PG1_LATCH    REG_BIT(21)
  #define  HOLD_PHY_PG1_LATCH           REG_BIT(20)
  #define  DC_STATE_EN_UPTO_DC5         (1 << 0)
  #define  DC_STATE_EN_DC9              (1 << 3)
  #define  DC_STATE_EN_UPTO_DC6         (2 << 0)
+#define  DC_STATE_EN_UPTO_DC3CO                (3 << 0)

This could use a conversion to REG_FIELD_MASK and REG_FIELD_PREP.

  #define  DC_STATE_EN_UPTO_DC5_DC6_MASK   0x3

#define DC_STATE_DEBUG _MMIO(0x45520)

diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.c 
b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
index 73a3101514f3..9f403b7820ab 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc_wl.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
@@ -260,7 +260,7 @@ static bool intel_dmc_wl_check_range(struct intel_display 
*display,
         * the DMC and requires a DC exit for proper access.
         */
        switch (dc_state) {
-       case DC_STATE_EN_DC3CO:
+       case DC_STATE_EN_UPTO_DC3CO:
                ranges = xe3lpd_dc3co_dmc_ranges;
                break;
        case DC_STATE_EN_UPTO_DC5: