On 05-01-2026 18:32, Jani Nikula wrote:
On Tue, 09 Dec 2025, Dibin Moolakadan
Subrahmanian<[email protected]> wrote:
if DC3CO allowed and psr2 is enabled, update dc3co_source
Yeah, I can read the code, but what does it mean? Why?
I will add more details.
The intent is to record PSR2 as the source enabling DC3CO.
DC3CO can be entered when either PSR2 or LOBF is enabled, and
dc3co_source is used to track which feature triggered it.
Signed-off-by: Dibin Moolakadan
Subrahmanian<[email protected]>
---
drivers/gpu/drm/i915/display/intel_psr.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 9c616f449ad6..d4c5dc6dcc82 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -3007,6 +3007,12 @@ void intel_psr_post_plane_update(struct
intel_atomic_state *state,
if (crtc_state->crc_enabled && psr->enabled)
intel_psr_force_update(intel_dp);
+ if (psr->enabled &&
+ psr->sel_update_enabled &&
+ intel_dc3co_allowed(display)) {
+ intel_dc3co_source_set(display, DC3CO_SOURCE_PSR2);
+ }
+
/*
* Clear possible busy bits in case we have
* invalidate -> flip -> flush sequence.
