On Thu, 22 Jan 2026, Uma Shankar <[email protected]> wrote: > There are certain register definitions which are defined in i915_reg.h > which are exclusively needed by display. Move the same to display > headers to remove i915_reg.h includes from display. This is a step > towards making display independent of i915. > > intel_clock_gating.c can include display header directly. > > v2: Drop common header in include and use display_regs.h (Jani) > > Signed-off-by: Uma Shankar <[email protected]>
Oh, the Subject should just be drm/i915, this isn't directly related to xe. > --- > drivers/gpu/drm/i915/display/intel_display_regs.h | 10 ++++++++++ > drivers/gpu/drm/i915/display/intel_pch_display.c | 1 - > drivers/gpu/drm/i915/i915_reg.h | 10 ---------- > drivers/gpu/drm/i915/intel_clock_gating.c | 2 +- > 4 files changed, 11 insertions(+), 12 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h > b/drivers/gpu/drm/i915/display/intel_display_regs.h > index 9e0d853f4b61..9f8fbfb2e115 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_regs.h > +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h > @@ -2021,6 +2021,16 @@ > #define TRANS_BPC_6 REG_FIELD_PREP(TRANS_BPC_MASK, 2) > #define TRANS_BPC_12 REG_FIELD_PREP(TRANS_BPC_MASK, > 3) > > +#define _TRANSA_CHICKEN2 0xf0064 > +#define _TRANSB_CHICKEN2 0xf1064 > +#define TRANS_CHICKEN2(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, > _TRANSB_CHICKEN2) > +#define TRANS_CHICKEN2_TIMING_OVERRIDE REG_BIT(31) > +#define TRANS_CHICKEN2_FDI_POLARITY_REVERSED REG_BIT(29) > +#define TRANS_CHICKEN2_FRAME_START_DELAY_MASK REG_GENMASK(28, > 27) > +#define TRANS_CHICKEN2_FRAME_START_DELAY(x) > REG_FIELD_PREP(TRANS_CHICKEN2_FRAME_START_DELAY_MASK, (x)) /* 0-3 */ > +#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER REG_BIT(26) > +#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH REG_BIT(25) > + > #define PCH_DP_B _MMIO(0xe4100) > #define PCH_DP_C _MMIO(0xe4200) > #define PCH_DP_D _MMIO(0xe4300) > diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c > b/drivers/gpu/drm/i915/display/intel_pch_display.c > index 16619f7be5f8..69c7952a1413 100644 > --- a/drivers/gpu/drm/i915/display/intel_pch_display.c > +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c > @@ -6,7 +6,6 @@ > #include <drm/drm_print.h> > > #include "g4x_dp.h" > -#include "i915_reg.h" > #include "intel_crt.h" > #include "intel_crt_regs.h" > #include "intel_de.h" > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 5bf3b4ab2baa..d247e107f42f 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1022,16 +1022,6 @@ > #define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE REG_BIT(10) > #define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE REG_BIT(4) > > -#define _TRANSA_CHICKEN2 0xf0064 > -#define _TRANSB_CHICKEN2 0xf1064 > -#define TRANS_CHICKEN2(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, > _TRANSB_CHICKEN2) > -#define TRANS_CHICKEN2_TIMING_OVERRIDE REG_BIT(31) > -#define TRANS_CHICKEN2_FDI_POLARITY_REVERSED REG_BIT(29) > -#define TRANS_CHICKEN2_FRAME_START_DELAY_MASK REG_GENMASK(28, > 27) > -#define TRANS_CHICKEN2_FRAME_START_DELAY(x) > REG_FIELD_PREP(TRANS_CHICKEN2_FRAME_START_DELAY_MASK, (x)) /* 0-3 */ > -#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER REG_BIT(26) > -#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH REG_BIT(25) > - > #define SOUTH_CHICKEN1 _MMIO(0xc2000) > #define FDIA_PHASE_SYNC_SHIFT_OVR 19 > #define FDIA_PHASE_SYNC_SHIFT_EN 18 > diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c > b/drivers/gpu/drm/i915/intel_clock_gating.c > index 7336934bb934..4e18d5a22112 100644 > --- a/drivers/gpu/drm/i915/intel_clock_gating.c > +++ b/drivers/gpu/drm/i915/intel_clock_gating.c > @@ -30,7 +30,7 @@ > #include "display/i9xx_plane_regs.h" > #include "display/intel_display.h" > #include "display/intel_display_core.h" > - > +#include "display/intel_display_regs.h" > #include "gt/intel_engine_regs.h" > #include "gt/intel_gt.h" > #include "gt/intel_gt_mcr.h" -- Jani Nikula, Intel
