On Thu, 22 Jan 2026, Uma Shankar <[email protected]> wrote: > Move common registers to display to allow intel_display_rps.c > free of i915_reg.h dependency.
The grammar's not quite right there. > Signed-off-by: Uma Shankar <[email protected]> > --- > .../gpu/drm/i915/display/intel_display_regs.h | 34 +++++++++++++++++++ > .../gpu/drm/i915/display/intel_display_rps.c | 2 +- > drivers/gpu/drm/i915/i915_reg.h | 33 ------------------ > 3 files changed, 35 insertions(+), 34 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h > b/drivers/gpu/drm/i915/display/intel_display_regs.h > index 4759a9600d3f..1f922d013cd3 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_regs.h > +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h > @@ -1333,6 +1333,40 @@ > GEN8_DE_PORT_IER, \ > GEN8_DE_PORT_IIR) > > +/* interrupts */ > +#define DE_MASTER_IRQ_CONTROL (1 << 31) > +#define DE_SPRITEB_FLIP_DONE (1 << 29) > +#define DE_SPRITEA_FLIP_DONE (1 << 28) > +#define DE_PLANEB_FLIP_DONE (1 << 27) > +#define DE_PLANEA_FLIP_DONE (1 << 26) > +#define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane))) > +#define DE_PCU_EVENT (1 << 25) > +#define DE_GTT_FAULT (1 << 24) > +#define DE_POISON (1 << 23) > +#define DE_PERFORM_COUNTER (1 << 22) > +#define DE_PCH_EVENT (1 << 21) > +#define DE_AUX_CHANNEL_A (1 << 20) > +#define DE_DP_A_HOTPLUG (1 << 19) > +#define DE_GSE (1 << 18) > +#define DE_PIPEB_VBLANK (1 << 15) > +#define DE_PIPEB_EVEN_FIELD (1 << 14) > +#define DE_PIPEB_ODD_FIELD (1 << 13) > +#define DE_PIPEB_LINE_COMPARE (1 << 12) > +#define DE_PIPEB_VSYNC (1 << 11) > +#define DE_PIPEB_CRC_DONE (1 << 10) > +#define DE_PIPEB_FIFO_UNDERRUN (1 << 8) > +#define DE_PIPEA_VBLANK (1 << 7) > +#define DE_PIPE_VBLANK(pipe) (1 << (7 + 8 * (pipe))) > +#define DE_PIPEA_EVEN_FIELD (1 << 6) > +#define DE_PIPEA_ODD_FIELD (1 << 5) > +#define DE_PIPEA_LINE_COMPARE (1 << 4) > +#define DE_PIPEA_VSYNC (1 << 3) > +#define DE_PIPEA_CRC_DONE (1 << 2) > +#define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8 * (pipe))) > +#define DE_PIPEA_FIFO_UNDERRUN (1 << 0) > +#define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8 * (pipe))) > + > + Superfluous newline. Other than that, Reviewed-by: Jani Nikula <[email protected]> PS. This one took like 5 seconds to review with 'git show --color-moved'. > #define GEN8_DE_MISC_ISR _MMIO(0x44460) > #define GEN8_DE_MISC_IMR _MMIO(0x44464) > #define GEN8_DE_MISC_IIR _MMIO(0x44468) > diff --git a/drivers/gpu/drm/i915/display/intel_display_rps.c > b/drivers/gpu/drm/i915/display/intel_display_rps.c > index e77811396474..bf00266dae4b 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_rps.c > +++ b/drivers/gpu/drm/i915/display/intel_display_rps.c > @@ -8,8 +8,8 @@ > #include <drm/drm_crtc.h> > #include <drm/drm_vblank.h> > > -#include "i915_reg.h" > #include "intel_display_core.h" > +#include "intel_display_regs.h" > #include "intel_display_irq.h" > #include "intel_display_rps.h" > #include "intel_display_types.h" > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 80ea0df40b1e..5cd124083c17 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -804,39 +804,6 @@ > #define RM_TIMEOUT_REG_CAPTURE _MMIO(0x420E0) > #define MMIO_TIMEOUT_US(us) ((us) << 0) > > -/* interrupts */ > -#define DE_MASTER_IRQ_CONTROL (1 << 31) > -#define DE_SPRITEB_FLIP_DONE (1 << 29) > -#define DE_SPRITEA_FLIP_DONE (1 << 28) > -#define DE_PLANEB_FLIP_DONE (1 << 27) > -#define DE_PLANEA_FLIP_DONE (1 << 26) > -#define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane))) > -#define DE_PCU_EVENT (1 << 25) > -#define DE_GTT_FAULT (1 << 24) > -#define DE_POISON (1 << 23) > -#define DE_PERFORM_COUNTER (1 << 22) > -#define DE_PCH_EVENT (1 << 21) > -#define DE_AUX_CHANNEL_A (1 << 20) > -#define DE_DP_A_HOTPLUG (1 << 19) > -#define DE_GSE (1 << 18) > -#define DE_PIPEB_VBLANK (1 << 15) > -#define DE_PIPEB_EVEN_FIELD (1 << 14) > -#define DE_PIPEB_ODD_FIELD (1 << 13) > -#define DE_PIPEB_LINE_COMPARE (1 << 12) > -#define DE_PIPEB_VSYNC (1 << 11) > -#define DE_PIPEB_CRC_DONE (1 << 10) > -#define DE_PIPEB_FIFO_UNDERRUN (1 << 8) > -#define DE_PIPEA_VBLANK (1 << 7) > -#define DE_PIPE_VBLANK(pipe) (1 << (7 + 8 * (pipe))) > -#define DE_PIPEA_EVEN_FIELD (1 << 6) > -#define DE_PIPEA_ODD_FIELD (1 << 5) > -#define DE_PIPEA_LINE_COMPARE (1 << 4) > -#define DE_PIPEA_VSYNC (1 << 3) > -#define DE_PIPEA_CRC_DONE (1 << 2) > -#define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8 * (pipe))) > -#define DE_PIPEA_FIFO_UNDERRUN (1 << 0) > -#define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8 * (pipe))) > - > #define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master > IER */ > #define MASTER_INTERRUPT_ENABLE (1 << 31) -- Jani Nikula, Intel
