On Thu, 22 Jan 2026, Uma Shankar <[email protected]> wrote: > Make intel_rom.c free from including i915_reg.h. > > v2: Use display header instead of gmd common include (Jani) > > Signed-off-by: Uma Shankar <[email protected]>
Reviewed-by: Jani Nikula <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_display_regs.h | 8 ++++++++ > drivers/gpu/drm/i915/display/intel_rom.c | 3 +-- > drivers/gpu/drm/i915/i915_reg.h | 8 -------- > 3 files changed, 9 insertions(+), 10 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h > b/drivers/gpu/drm/i915/display/intel_display_regs.h > index 2c7cd9002da3..f468e0d20b92 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_regs.h > +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h > @@ -9,6 +9,14 @@ > #define GU_CNTL_PROTECTED _MMIO(0x10100C) > #define DEPRESENT REG_BIT(9) > > +#define PRIMARY_SPI_TRIGGER _MMIO(0x102040) > +#define PRIMARY_SPI_ADDRESS _MMIO(0x102080) > +#define PRIMARY_SPI_REGIONID _MMIO(0x102084) > +#define SPI_STATIC_REGIONS _MMIO(0x102090) > +#define OPTIONROM_SPI_REGIONID_MASK REG_GENMASK(7, 0) > +#define OROM_OFFSET _MMIO(0x1020c0) > +#define OROM_OFFSET_MASK REG_GENMASK(20, 16) > + > #define _GEN7_PIPEA_DE_LOAD_SL 0x70068 > #define _GEN7_PIPEB_DE_LOAD_SL 0x71068 > #define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, > _GEN7_PIPEB_DE_LOAD_SL) > diff --git a/drivers/gpu/drm/i915/display/intel_rom.c > b/drivers/gpu/drm/i915/display/intel_rom.c > index c8f615315310..d7de53acaba9 100644 > --- a/drivers/gpu/drm/i915/display/intel_rom.c > +++ b/drivers/gpu/drm/i915/display/intel_rom.c > @@ -7,10 +7,9 @@ > > #include <drm/drm_device.h> > > -#include "i915_reg.h" > - > #include "intel_rom.h" > #include "intel_uncore.h" > +#include "intel_display_regs.h" > > struct intel_rom { > /* for PCI ROM */ > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 5d640f7cfc23..d43c04e491e1 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -892,14 +892,6 @@ > #define SGGI_DIS REG_BIT(15) > #define SGR_DIS REG_BIT(13) > > -#define PRIMARY_SPI_TRIGGER _MMIO(0x102040) > -#define PRIMARY_SPI_ADDRESS _MMIO(0x102080) > -#define PRIMARY_SPI_REGIONID _MMIO(0x102084) > -#define SPI_STATIC_REGIONS _MMIO(0x102090) > -#define OPTIONROM_SPI_REGIONID_MASK REG_GENMASK(7, 0) > -#define OROM_OFFSET _MMIO(0x1020c0) > -#define OROM_OFFSET_MASK REG_GENMASK(20, 16) > - > #define MTL_MEDIA_GSI_BASE 0x380000 > > #endif /* _I915_REG_H_ */ -- Jani Nikula, Intel
