> > Subject: [PATCH v2 1/1] drm/i915/display: Implement Wa_16024710867 > > > > Defeature port sync feature for xe3lpd onwards. > > > > --v1: > > - Use xe3lpd naming (Suraj) > > - Use IS_DISPLAY_VER (Suraj) > > > > Signed-off-by: Mitul Golani <[email protected]> > > --- > > drivers/gpu/drm/i915/display/intel_ddi.c | 5 ++++- > > 1 file changed, 4 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c > > b/drivers/gpu/drm/i915/display/intel_ddi.c > > index d8739e2bb004..a3e6f9a31b20 100644 > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > > @@ -4588,8 +4588,11 @@ intel_ddi_port_sync_transcoders(const struct > > intel_crtc_state *ref_crtc_state, > > /* > > * We don't enable port sync on BDW due to missing w/as and > > * due to not having adjusted the modeset sequence appropriately. > > + * > > + * Wa_16024710867 > > + * Deprecate port sync support for xe3lpd+ > > */ > > - if (DISPLAY_VER(display) < 9) > > + if (!IS_DISPLAY_VER(display, 9, 20)) > > return 0; > > > I guess instead of 20 it should be 30.
No it wouldn't be since the range we want is from [9, 30) where 30 is not included so it would ideally be (9,29) But since we jump from display ver 20 to 30 it would be IS_DISPLAY_VER(9,20) Regards, Suraj Kandpal > > Regards, > Nemesa > > if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP)) > > -- > > 2.48.1
