Program CMTG Clk Select. v2: - Correct mask for PHY B. [Jani] - Use REG_FIELD_PREP() for enable value. [Dibin] - Extend cmtg clock select for xe3plpd. [Dibin]
Signed-off-by: Animesh Manna <[email protected]> Signed-off-by: Dibin Moolakadan Subrahmanian <[email protected]> --- drivers/gpu/drm/i915/display/intel_cmtg.c | 22 +++++++++++++++++++ drivers/gpu/drm/i915/display/intel_cmtg.h | 2 ++ .../gpu/drm/i915/display/intel_cmtg_regs.h | 2 ++ drivers/gpu/drm/i915/display/intel_cx0_phy.c | 5 +++++ drivers/gpu/drm/i915/display/intel_lt_phy.c | 9 ++++++-- 5 files changed, 38 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c index e1fdc6fe9762..f5364f5a848f 100644 --- a/drivers/gpu/drm/i915/display/intel_cmtg.c +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c @@ -16,6 +16,7 @@ #include "intel_display_device.h" #include "intel_display_power.h" #include "intel_display_regs.h" +#include "intel_display_types.h" /** * DOC: Common Primary Timing Generator (CMTG) @@ -185,3 +186,24 @@ void intel_cmtg_sanitize(struct intel_display *display) intel_cmtg_disable(display, &cmtg_config); } + +void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; + u32 clk_sel_clr = 0; + u32 clk_sel_set = 0; + + if (cpu_transcoder == TRANSCODER_A) { + clk_sel_clr = CMTG_CLK_SEL_A_MASK; + clk_sel_set = CMTG_CLK_SELECT_PHYA_ENABLE; + } + + if (cpu_transcoder == TRANSCODER_B) { + clk_sel_clr = CMTG_CLK_SEL_B_MASK; + clk_sel_set = CMTG_CLK_SELECT_PHYB_ENABLE; + } + + if (clk_sel_set) + intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr, clk_sel_set); +} diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h index ba62199adaa2..bef2426b2787 100644 --- a/drivers/gpu/drm/i915/display/intel_cmtg.h +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h @@ -7,7 +7,9 @@ #define __INTEL_CMTG_H__ struct intel_display; +struct intel_crtc_state; +void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state); void intel_cmtg_sanitize(struct intel_display *display); #endif /* __INTEL_CMTG_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h index 945a35578284..8a767b659a23 100644 --- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h +++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h @@ -10,8 +10,10 @@ #define CMTG_CLK_SEL _MMIO(0x46160) #define CMTG_CLK_SEL_A_MASK REG_GENMASK(31, 29) +#define CMTG_CLK_SELECT_PHYA_ENABLE REG_FIELD_PREP(CMTG_CLK_SEL_A_MASK, 0x4) #define CMTG_CLK_SEL_A_DISABLED REG_FIELD_PREP(CMTG_CLK_SEL_A_MASK, 0) #define CMTG_CLK_SEL_B_MASK REG_GENMASK(15, 13) +#define CMTG_CLK_SELECT_PHYB_ENABLE REG_FIELD_PREP(CMTG_CLK_SEL_A_MASK, 0x6) #define CMTG_CLK_SEL_B_DISABLED REG_FIELD_PREP(CMTG_CLK_SEL_B_MASK, 0) #define TRANS_CMTG_CTL_A _MMIO(0x6fa88) diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index 6a471c021c0e..a88f013e472b 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -9,6 +9,7 @@ #include <drm/drm_print.h> #include "intel_alpm.h" +#include "intel_cmtg.h" #include "intel_cx0_phy.h" #include "intel_cx0_phy_regs.h" #include "intel_display_regs.h" @@ -3417,9 +3418,13 @@ void intel_mtl_pll_enable_clock(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { struct intel_digital_port *dig_port = enc_to_dig_port(encoder); + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); if (intel_tc_port_in_tbt_alt_mode(dig_port)) intel_mtl_tbt_pll_enable_clock(encoder, crtc_state->port_clock); + + if (crtc->cmtg.enable) + intel_cmtg_set_clk_select(crtc_state); } /* diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c index 04f63bdd0b87..f6c45bf9d0f3 100644 --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c @@ -6,6 +6,7 @@ #include <drm/drm_print.h> #include "i915_reg.h" +#include "intel_cmtg.h" #include "intel_cx0_phy.h" #include "intel_cx0_phy_regs.h" #include "intel_ddi.h" @@ -2246,11 +2247,15 @@ void intel_xe3plpd_pll_enable(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { struct intel_digital_port *dig_port = enc_to_dig_port(encoder); + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - if (intel_tc_port_in_tbt_alt_mode(dig_port)) + if (intel_tc_port_in_tbt_alt_mode(dig_port)) { intel_mtl_tbt_pll_enable_clock(encoder, crtc_state->port_clock); - else + } else { intel_lt_phy_pll_enable(encoder, crtc_state); + if (crtc->cmtg.enable) + intel_cmtg_set_clk_select(crtc_state); + } } void intel_xe3plpd_pll_disable(struct intel_encoder *encoder) -- 2.29.0
