Matt Roper <[email protected]> writes:
> On Mon, Feb 02, 2026 at 06:43:08PM -0300, Gustavo Sousa wrote:
>> From: Shekhar Chauhan <[email protected]>
>>
>> Add the initial set of workarounds for Xe3p_LPG graphics version 35.10.
>>
>> Signed-off-by: Shekhar Chauhan <[email protected]>
>> Co-developed-by: Nitin Gote <[email protected]>
>> Signed-off-by: Nitin Gote <[email protected]>
>> Co-developed-by: Tangudu Tilak Tirumalesh
>> <[email protected]>
>> Signed-off-by: Tangudu Tilak Tirumalesh <[email protected]>
>> Co-developed-by: Mallesh Koujalagi <[email protected]>
>> Signed-off-by: Mallesh Koujalagi <[email protected]>
>> Co-developed-by: Gustavo Sousa <[email protected]>
>> Signed-off-by: Gustavo Sousa <[email protected]>
>> ---
>> drivers/gpu/drm/xe/regs/xe_gt_regs.h | 19 ++++++++++++++
>> drivers/gpu/drm/xe/xe_reg_whitelist.c | 8 ++++++
>> drivers/gpu/drm/xe/xe_wa.c | 48
>> +++++++++++++++++++++++++++++++++++
>> 3 files changed, 75 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> index 24fc64fc832e..b5a7cc45f13d 100644
>> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> @@ -100,6 +100,9 @@
>> #define VE1_AUX_INV XE_REG(0x42b8)
>> #define AUX_INV REG_BIT(0)
>>
>> +#define GAMSTLB_CTRL2 XE_REG_MCR(0x4788)
>> +#define STLB_SINGLE_BANK_MODE REG_BIT(11)
>> +
>> #define XE2_LMEM_CFG XE_REG(0x48b0)
>>
>> #define XE2_GAMWALK_CTRL 0x47e4
>> @@ -107,12 +110,18 @@
>> #define XE2_GAMWALK_CTRL_3D XE_REG_MCR(XE2_GAMWALK_CTRL)
>> #define EN_CMP_1WCOH_GW REG_BIT(14)
>>
>> +#define MMIOATSREQLIMIT_GAM_WALK_3D XE_REG_MCR(0x47f8)
>> +#define DIS_ATS_WRONLY_PG REG_BIT(18)
>> +
>> #define XEHP_FLAT_CCS_BASE_ADDR XE_REG_MCR(0x4910)
>> #define XEHP_FLAT_CCS_PTR REG_GENMASK(31, 8)
>>
>> #define WM_CHICKEN3 XE_REG_MCR(0x5588,
>> XE_REG_OPTION_MASKED)
>> #define HIZ_PLANE_COMPRESSION_DIS REG_BIT(10)
>>
>> +#define TBIMR_MODE XE_REG_MCR(0x6200,
>> XE_REG_OPTION_MASKED)
>> +#define RXBAR_NO_UAV_DEC_SYNC REG_BIT(12)
>> +
>> #define CHICKEN_RASTER_1 XE_REG_MCR(0x6204,
>> XE_REG_OPTION_MASKED)
>> #define DIS_SF_ROUND_NEAREST_EVEN REG_BIT(8)
>> #define DIS_CLIP_NEGATIVE_BOUNDING_BOX REG_BIT(6)
>> @@ -210,6 +219,9 @@
>>
>> #define GSCPSMI_BASE XE_REG(0x880c)
>>
>> +#define CCCHKNREG2 XE_REG_MCR(0x881c)
>> +#define LOCALITYDIS REG_BIT(7)
>
> Nitpick: the formatting is slightly off here (the field name should be
> spaced over one more column).
>
>> +
>> #define CCCHKNREG1 XE_REG_MCR(0x8828)
>> #define L3CMPCTRL REG_BIT(23)
>> #define ENCOMPPERFFIX REG_BIT(18)
>> @@ -420,6 +432,8 @@
>> #define LSN_DIM_Z_WGT(value)
>> REG_FIELD_PREP(LSN_DIM_Z_WGT_MASK, value)
>>
>> #define L3SQCREG2 XE_REG_MCR(0xb104)
>> +#define L3_SQ_DISABLE_COAMA_2WAY_COH REG_BIT(30)
>> +#define L3_SQ_DISABLE_COAMA REG_BIT(22)
>> #define COMPMEMRD256BOVRFETCHEN REG_BIT(20)
>>
>> #define L3SQCREG3 XE_REG_MCR(0xb108)
>> @@ -550,11 +564,16 @@
>> #define UGM_FRAGMENT_THRESHOLD_TO_3 REG_BIT(58 - 32)
>> #define DIS_CHAIN_2XSIMD8 REG_BIT(55 - 32)
>> #define XE2_ALLOC_DPA_STARVE_FIX_DIS REG_BIT(47 - 32)
>> +#define SAMPLER_LD_LSC_DISABLE REG_BIT(45 - 32)
>> #define ENABLE_SMP_LD_RENDER_SURFACE_CONTROL REG_BIT(44 - 32)
>> #define FORCE_SLM_FENCE_SCOPE_TO_TILE REG_BIT(42 - 32)
>> #define FORCE_UGM_FENCE_SCOPE_TO_TILE REG_BIT(41 - 32)
>> #define MAXREQS_PER_BANK REG_GENMASK(39 - 32, 37 - 32)
>> #define DISABLE_128B_EVICTION_COMMAND_UDW REG_BIT(36 - 32)
>> +#define LSCFE_SAME_ADDRESS_ATOMICS_COALESCING_DISABLE REG_BIT(35 - 32)
>> +
>> +#define ROW_CHICKEN5 XE_REG_MCR(0xe7f0)
>> +#define CPSS_AWARE_DIS REG_BIT(3)
>>
>> #define SARB_CHICKEN1 XE_REG_MCR(0xe90c)
>> #define COMP_CKN_IN REG_GENMASK(30, 29)
>> diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c
>> b/drivers/gpu/drm/xe/xe_reg_whitelist.c
>> index 1d36c09681aa..9c513778d370 100644
>> --- a/drivers/gpu/drm/xe/xe_reg_whitelist.c
>> +++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c
>> @@ -81,6 +81,14 @@ static const struct xe_rtp_entry_sr register_whitelist[]
>> = {
>> WHITELIST(VFLSKPD,
>> RING_FORCE_TO_NONPRIV_ACCESS_RW))
>> },
>> + { XE_RTP_NAME("14024997852"),
>> + XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0),
>> + ENGINE_CLASS(RENDER)),
>> + XE_RTP_ACTIONS(WHITELIST(FF_MODE,
>> + RING_FORCE_TO_NONPRIV_ACCESS_RW),
>> + WHITELIST(VFLSKPD,
>> + RING_FORCE_TO_NONPRIV_ACCESS_RW))
>> + },
>>
>> #define WHITELIST_OA_MMIO_TRG(trg, status, head) \
>> WHITELIST(trg, RING_FORCE_TO_NONPRIV_ACCESS_RW), \
>> diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
>> index a991ee2b8781..68a494743b34 100644
>> --- a/drivers/gpu/drm/xe/xe_wa.c
>> +++ b/drivers/gpu/drm/xe/xe_wa.c
>> @@ -306,6 +306,31 @@ static const struct xe_rtp_entry_sr gt_was[] = {
>> XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3005)),
>> XE_RTP_ACTIONS(SET(GUC_INTR_CHICKEN, DISABLE_SIGNALING_ENGINES))
>> },
>> +
>> + /* Xe3P_LPG */
>> +
>> + { XE_RTP_NAME("14025160223"),
>> + XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0)),
>> + XE_RTP_ACTIONS(SET(MMIOATSREQLIMIT_GAM_WALK_3D,
>> + DIS_ATS_WRONLY_PG))
>> + },
>> + { XE_RTP_NAME("16028780921"),
>> + XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0)),
>> + XE_RTP_ACTIONS(SET(CCCHKNREG2, LOCALITYDIS))
>> + },
>> + { XE_RTP_NAME("14026144927"),
>> + XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0)),
>> + XE_RTP_ACTIONS(SET(L3SQCREG2, L3_SQ_DISABLE_COAMA_2WAY_COH |
>> + L3_SQ_DISABLE_COAMA))
>> + },
>> + { XE_RTP_NAME("14025635424"),
>> + XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0)),
>> + XE_RTP_ACTIONS(SET(GAMSTLB_CTRL2, STLB_SINGLE_BANK_MODE))
>> + },
>> + { XE_RTP_NAME("16028005424"),
>> + XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0)),
>> + XE_RTP_ACTIONS(SET(GUC_INTR_CHICKEN, DISABLE_SIGNALING_ENGINES))
>> + },
>> };
>>
>> static const struct xe_rtp_entry_sr engine_was[] = {
>> @@ -680,6 +705,24 @@ static const struct xe_rtp_entry_sr engine_was[] = {
>> FUNC(xe_rtp_match_gt_has_discontiguous_dss_groups)),
>> XE_RTP_ACTIONS(SET(TDL_CHICKEN, EUSTALL_PERF_SAMPLING_DISABLE))
>> },
>> +
>> + /* Xe3p_LPG*/
>> +
>> + { XE_RTP_NAME("22021149932"),
>> + XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0),
>> + FUNC(xe_rtp_match_first_render_or_compute)),
>> + XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, SAMPLER_LD_LSC_DISABLE))
>> + },
>> + { XE_RTP_NAME("14025676848"),
>> + XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0),
>> + FUNC(xe_rtp_match_first_render_or_compute)),
>> + XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW,
>> LSCFE_SAME_ADDRESS_ATOMICS_COALESCING_DISABLE))
>> + },
>> + { XE_RTP_NAME("16028951944"),
>> + XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0),
>> + FUNC(xe_rtp_match_first_render_or_compute)),
>> + XE_RTP_ACTIONS(SET(ROW_CHICKEN5, CPSS_AWARE_DIS))
>> + },
>> };
>>
>> static const struct xe_rtp_entry_sr lrc_was[] = {
>> @@ -879,6 +922,11 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
>> ENGINE_CLASS(RENDER)),
>> XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_CLIP_NEGATIVE_BOUNDING_BOX))
>> },
>> + { XE_RTP_NAME("14025780377"),
>> + XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0),
>> + ENGINE_CLASS(RENDER)),
>> + XE_RTP_ACTIONS(SET(TBIMR_MODE, RXBAR_NO_UAV_DEC_SYNC))
>
> I'm not sure if this one is actually needed. Originally the workaround
> ticket just said "program 0x6200[12]" but it's since been updated to an
> "if (por) no workaround needed, else if (non-POR thing) program the
> register and add a stalling flush." There are also comments in the
> ticket itself that indicate it shouldn't actually be relevant to this
> specific platform due to other characteristics of the platform; it's
> just something that they'll need to fix or workaround in the future so
> that it doesn't impact future derivative platforms.
Incorporated feedback and they will be in v2 of this series.
Thanks!
Gustavo Sousa
>
>
> Matt
>
>> + },
>> };
>>
>> static __maybe_unused const struct xe_rtp_entry oob_was[] = {
>>
>> --
>> 2.52.0
>>
>
> --
> Matt Roper
> Graphics Software Engineer
> Linux GPU Platform Enablement
> Intel Corporation
