> -----Original Message----- > From: Intel-xe <[email protected]> On Behalf Of Gustavo > Sousa > Sent: Tuesday, February 3, 2026 3:13 AM > To: [email protected]; [email protected] > Cc: Sousa, Gustavo <[email protected]>; Roper, Matthew D > <[email protected]> > Subject: [PATCH 09/16] drm/xe/xe3p_lpg: Extend 'group ID' mask size > > From: Matt Roper <[email protected]> > > Xe3p_LPG extends the 'group ID' register mask by one bit. Since the new upper > bit (12) was unused on previous platforms, we can safely extend the existing > mask > size without worrying about adding conditional version checks to the register > programming. > > Bspec: 67175 > Signed-off-by: Matt Roper <[email protected]> > Signed-off-by: Gustavo Sousa <[email protected]>
LGTM, Reviewed-by: Dnyaneshwar Bhadane <[email protected]> > --- > drivers/gpu/drm/xe/regs/xe_gt_regs.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h > b/drivers/gpu/drm/xe/regs/xe_gt_regs.h > index b5a7cc45f13d..19f053a7f9be 100644 > --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h > +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h > @@ -58,7 +58,7 @@ > #define MCR_SLICE(slice) > REG_FIELD_PREP(MCR_SLICE_MASK, slice) > #define MCR_SUBSLICE_MASK REG_GENMASK(26, 24) > #define MCR_SUBSLICE(subslice) > REG_FIELD_PREP(MCR_SUBSLICE_MASK, subslice) > -#define MTL_MCR_GROUPID REG_GENMASK(11, 8) > +#define MTL_MCR_GROUPID REG_GENMASK(12, 8) > #define MTL_MCR_INSTANCEID REG_GENMASK(3, 0) > > #define PS_INVOCATION_COUNT XE_REG(0x2348) > > -- > 2.52.0
