> Subject: [PATCH v2 06/10] drm/i915/cmtg: set transcoder mn for cmtg * CMTG
> > Program CMTG link M/N. > Bspec link > Signed-off-by: Animesh Manna <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_cmtg.c | 12 ++++++++++++ > drivers/gpu/drm/i915/display/intel_cmtg_regs.h | 3 +++ > 2 files changed, 15 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c > b/drivers/gpu/drm/i915/display/intel_cmtg.c > index cb1376f4c13f..12a081dd7e4d 100644 > --- a/drivers/gpu/drm/i915/display/intel_cmtg.c > +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c > @@ -234,6 +234,16 @@ static void intel_cmtg_set_timings(const struct > intel_crtc_state *crtc_state) > } > } > > +static void intel_cpu_cmtg_transcoder_set_m_n(const struct Should be intel_cmtg_transcoder_set_m_n Regards, Suraj Kandpal > +intel_crtc_state *crtc_state) { > + struct intel_display *display = to_intel_display(crtc_state); > + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; > + const struct intel_link_m_n *m_n = &crtc_state->dp_m_n; > + > + intel_de_write(display, TRANS_LINKM1_CMTG(cpu_transcoder), m_n- > >link_m); > + intel_de_write(display, TRANS_LINKN1_CMTG(cpu_transcoder), > +m_n->link_n); } > + > void intel_cmtg_enable(const struct intel_crtc_state *crtc_state) { > struct intel_display *display = to_intel_display(crtc_state); @@ -246,4 > +256,6 @@ void intel_cmtg_enable(const struct intel_crtc_state *crtc_state) > > intel_de_write(display, > TRANS_SET_CTX_LATENCY_CMTG(cpu_transcoder), > intel_de_read(display, > TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder))); > + > + intel_cpu_cmtg_transcoder_set_m_n(crtc_state); > } > diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h > b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h > index 3cfd8eedb321..b766ded8686c 100644 > --- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h > +++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h > @@ -32,6 +32,9 @@ > #define TRANS_VRR_VMIN_CMTG(id) _MMIO(0x6F434 + (id) * > 0x100) > #define TRANS_VRR_FLIPLINE_CMTG(id) _MMIO(0x6F438 + (id) * > 0x100) > > +#define TRANS_LINKM1_CMTG(id) _MMIO(0x6F040 + (id) * 0x100) > +#define TRANS_LINKN1_CMTG(id) _MMIO(0x6F044 + (id) * 0x100) > + > #define TRANS_SET_CTX_LATENCY_CMTG(id) _MMIO(0x6F07C + (id) * > 0x100) > > #endif /* __INTEL_CMTG_REGS_H__ */ > -- > 2.29.0
