Hello Austin,
On 2/10/2026 3:04 AM, Austin Hu wrote:
Verified on PTL, where IGT case kms_color_pipeline passes for PipeA
and PipeB.
Though I am replying to this patch. My thoughts are for the overall series.
3DLUT cannot be added to *PLANE* color pipeline for platforms before
NVL. This gives the user-space false information that 3D LUT operates in
the pre-blend pipeline while it actually lies in the post-blend pipeline.
It will be eventually added to *PIPE* color pipeline in works here[1].
Regarding exposing the 3DLUT on multiple planes (and on the CRTC), since
there is only one 3DLUT per pipe, we need to reject userspace requests
that attempt to enable the 3DLUT simultaneously at different stages of
the pipeline. To keep things simple, we exposed the 3DLUT only on the
primary plane. More details can be found in [2]. This will change once
the 3DLUT is also exposed through the *PIPE* color pipeline.
[1]
https://lore.kernel.org/dri-devel/20251223-mtk-post-blend-color-pipeline-v3-0-7d969f9a3...@collabora.com/
[2]
https://lore.kernel.org/dri-devel/[email protected]/
==
Chaitanya
Signed-off-by: Austin Hu <[email protected]>
---
drivers/gpu/drm/i915/display/intel_color_pipeline.c | 5 ++---
drivers/gpu/drm/i915/display/intel_display_device.c | 6 ++++++
drivers/gpu/drm/i915/display/intel_display_device.h | 2 ++
drivers/gpu/drm/i915/display/intel_display_regs.h | 1 +
4 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color_pipeline.c
b/drivers/gpu/drm/i915/display/intel_color_pipeline.c
index 04af552b3..d26b0f134 100644
--- a/drivers/gpu/drm/i915/display/intel_color_pipeline.c
+++ b/drivers/gpu/drm/i915/display/intel_color_pipeline.c
@@ -47,9 +47,8 @@ int _intel_color_pipeline_plane_init(struct drm_plane *plane,
struct drm_prop_en
drm_colorop_set_next_property(prev_op, &colorop->base);
prev_op = &colorop->base;
- if (DISPLAY_VER(display) >= 35 &&
- intel_color_crtc_has_3dlut(display, pipe) &&
- plane->type == DRM_PLANE_TYPE_PRIMARY) {
+ if ((DISPLAY_VER(display) >= 15) && HAS_3D_LUT(display) &&
+ intel_color_crtc_has_3dlut(display, pipe)) {
colorop = intel_colorop_create(INTEL_PLANE_CB_3DLUT);
ret = drm_plane_colorop_3dlut_init(dev, &colorop->base, plane, 17,
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c
b/drivers/gpu/drm/i915/display/intel_display_device.c
index 471f236c9..423f99a75 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -1908,6 +1908,12 @@ static void
__intel_display_device_info_runtime_init(struct intel_display *displ
if (display_runtime->num_scalers[pipe])
display_runtime->num_scalers[pipe] = 1;
}
+
+ if (REG_FIELD_GET(XE2LPD_DE_CAP_3DLUT_MASK, cap) ==
+ XE2LPD_DE_CAP_3DLUT_REMOVED)
+ display_runtime->has_3d_lut = false;
+ else
+ display_runtime->has_3d_lut = true;
}
if (DISPLAY_VER(display) >= 30)
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h
b/drivers/gpu/drm/i915/display/intel_display_device.h
index e84c190dc..f91ccca6b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -173,6 +173,7 @@ struct intel_display_platforms {
#define HAS_DSC(__display)
(DISPLAY_RUNTIME_INFO(__display)->has_dsc)
#define HAS_DSC_3ENGINES(__display) (DISPLAY_VERx100(__display) == 1401 &&
HAS_DSC(__display))
#define HAS_DSC_MST(__display) (DISPLAY_VER(__display) >= 12
&& HAS_DSC(__display))
+#define HAS_3D_LUT(__display)
(DISPLAY_RUNTIME_INFO(__display)->has_3d_lut)
#define HAS_FBC(__display)
(DISPLAY_RUNTIME_INFO(__display)->fbc_mask != 0)
#define HAS_FBC_DIRTY_RECT(__display) (DISPLAY_VER(__display) >= 30)
#define HAS_FBC_SYS_CACHE(__display) (DISPLAY_VER(__display) >= 35 &&
!(__display)->platform.dgfx)
@@ -302,6 +303,7 @@ struct intel_display_runtime_info {
bool has_hdcp;
bool has_dmc;
bool has_dsc;
+ bool has_3d_lut;
bool edp_typec_support;
bool has_dbuf_overlap_detection;
};
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h
b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 9740f32ce..75fc7748a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -1554,6 +1554,7 @@
#define XE2LPD_DE_CAP _MMIO(0x41100)
#define XE2LPD_DE_CAP_3DLUT_MASK REG_GENMASK(31, 30)
+#define XE2LPD_DE_CAP_3DLUT_REMOVED 1
#define XE2LPD_DE_CAP_DSC_MASK REG_GENMASK(29, 28)
#define XE2LPD_DE_CAP_DSC_REMOVED 1
#define XE2LPD_DE_CAP_SCALER_MASK REG_GENMASK(27, 26)
