On Wed, 2014-04-09 at 13:28 +0300, ville.syrj...@linux.intel.com wrote: > From: Chon Ming Lee <chon.ming....@intel.com> > > Cherryview has 3 pipes. Some of the pll dpio offset calculation is > based on pipe number. Need to use vlv_pipe_to_channel to calculate the > correct phy channel to use for the pipe. > > Signed-off-by: Chon Ming Lee <chon.ming....@intel.com>
Reviewed-by: Imre Deak <imre.d...@intel.com>
> ---
> drivers/gpu/drm/i915/intel_drv.h | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index 087e471..e572799 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -544,6 +544,20 @@ vlv_dport_to_channel(struct intel_digital_port *dport)
> }
> }
>
> +static inline int
> +vlv_pipe_to_channel(enum pipe pipe)
> +{
> + switch (pipe) {
> + case PIPE_A:
> + case PIPE_C:
> + return DPIO_CH0;
> + case PIPE_B:
> + return DPIO_CH1;
> + default:
> + BUG();
> + }
> +}
> +
> static inline struct drm_crtc *
> intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
> {
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