On Wed, 2014-04-09 at 13:28 +0300, ville.syrj...@linux.intel.com wrote: > From: Chon Ming Lee <chon.ming....@intel.com> > > CHV has 2 display phys. First phy (IOSF offset 0x1A) has two channels, > and second phy (IOSF offset 0x12) has single channel. The first phy is > used for port B and port C, while second phy is only for port D. > > v2: Move the pipe to determine which phy to select for > vlv_dpio_read/vlv_dpio_write to another patch. (Daniel) > v3: Rebase the code based on rework on how to calculate DPIO offset. > > Signed-off-by: Chon Ming Lee <chon.ming....@intel.com>
Reviewed-by: Imre Deak <imre.d...@intel.com> > --- > drivers/gpu/drm/i915/i915_drv.h | 2 +- > drivers/gpu/drm/i915/i915_reg.h | 1 + > drivers/gpu/drm/i915/intel_display.c | 12 +++++++++++- > 3 files changed, 13 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 4abaa9e..07a162c 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -92,7 +92,7 @@ enum port { > }; > #define port_name(p) ((p) + 'A') > > -#define I915_NUM_PHYS_VLV 1 > +#define I915_NUM_PHYS_VLV 2 > > enum dpio_channel { > DPIO_CH0, > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index c7ec7d6..beb04ab 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -457,6 +457,7 @@ > #define IOSF_PORT_PUNIT 0x4 > #define IOSF_PORT_NC 0x11 > #define IOSF_PORT_DPIO 0x12 > +#define IOSF_PORT_DPIO_2 0x1a > #define IOSF_PORT_GPIO_NC 0x13 > #define IOSF_PORT_CCK 0x14 > #define IOSF_PORT_CCU 0xA9 > diff --git a/drivers/gpu/drm/i915/intel_display.c > b/drivers/gpu/drm/i915/intel_display.c > index 9a50b64..df6732e 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -1367,7 +1367,17 @@ static void intel_init_dpio(struct drm_device *dev) > if (!IS_VALLEYVIEW(dev)) > return; > > - DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO; > + /* > + * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C), > + * CHV x1 PHY (DP/HDMI D) > + * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C) > + */ > + if (IS_CHERRYVIEW(dev)) { > + DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2; > + DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO; > + } else { > + DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO; > + } > } > > static void intel_reset_dpio(struct drm_device *dev)
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