Baytail, like Sandybridge+, also has the RPS registers which are useful
to monitor. In addition, we were missing the evaluation interval
registers so add those to all.
Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_debugfs.c | 186 ++++++++++++++++++------------------
1 file changed, 94 insertions(+), 92 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index e8c4ddd9369b..c1741799d673 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1081,13 +1081,13 @@ static int i915_frequency_info(struct seq_file *m, void
*unused)
struct drm_info_node *node = m->private;
struct drm_device *dev = node->minor->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- int ret = 0;
intel_runtime_pm_get(dev_priv);
flush_delayed_work(&dev_priv->rps.delayed_resume_work);
-
- if (IS_GEN5(dev)) {
+ if (INTEL_INFO(dev)->gen < 5) {
+ seq_puts(m, "no P-state info available\n");
+ } else if (INTEL_INFO(dev)->gen < 6) {
u16 rgvswctl = I915_READ16(MEMSWCTL);
u16 rgvstat = I915_READ16(MEMSTAT_ILK);
@@ -1097,124 +1097,126 @@ static int i915_frequency_info(struct seq_file *m,
void *unused)
MEMSTAT_VID_SHIFT);
seq_printf(m, "Current P-state: %d\n",
(rgvstat & MEMSTAT_PSTATE_MASK) >>
MEMSTAT_PSTATE_SHIFT);
- } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
- IS_BROADWELL(dev)) {
- u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
- u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
- u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
+ } else {
u32 rpmodectl, rpinclimit, rpdeclimit;
- u32 rpstat, cagf, reqf;
- u32 rpupei, rpcurup, rpprevup;
- u32 rpdownei, rpcurdown, rpprevdown;
- int max_freq;
-
- /* RPSTAT1 is in the GT power well */
- ret = mutex_lock_interruptible(&dev->struct_mutex);
- if (ret)
- goto out;
+ u32 rpupei, rpcurupei, rpcurup, rpprevup;
+ u32 rpdownei, rpcurdownei, rpcurdown, rpprevdown;
gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
- reqf = I915_READ(GEN6_RPNSWREQ);
- reqf &= ~GEN6_TURBO_DISABLE;
- if (IS_HASWELL(dev) || IS_BROADWELL(dev))
- reqf >>= 24;
- else
- reqf >>= 25;
- reqf *= GT_FREQUENCY_MULTIPLIER;
+ if (IS_VALLEYVIEW(dev)) {
+ u32 freq_sts, val;
+
+ mutex_lock(&dev_priv->rps.hw_lock);
+ freq_sts = vlv_punit_read(dev_priv,
PUNIT_REG_GPU_FREQ_STS);
+ seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n",
freq_sts);
+ seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
+
+ val = valleyview_rps_max_freq(dev_priv);
+ seq_printf(m, "max GPU freq: %d MHz\n",
+ vlv_gpu_freq(dev_priv, val));
+
+ val = valleyview_rps_min_freq(dev_priv);
+ seq_printf(m, "min GPU freq: %d MHz\n",
+ vlv_gpu_freq(dev_priv, val));
+
+ seq_printf(m, "current GPU freq: %d MHz\n",
+ vlv_gpu_freq(dev_priv, (freq_sts >> 8) &
0xff));
+ mutex_unlock(&dev_priv->rps.hw_lock);
+ } else {
+ u32 gt_perf_status;
+ u32 rp_state_limits;
+ u32 rp_state_cap;
+ u32 cagf, reqf;
+ int max_freq;
+
+ gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
+ rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
+ rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
+
+ reqf = I915_READ(GEN6_RPNSWREQ);
+ reqf &= ~GEN6_TURBO_DISABLE;
+ if (IS_HASWELL(dev) || IS_BROADWELL(dev))
+ reqf >>= 24;
+ else
+ reqf >>= 25;
+ reqf *= GT_FREQUENCY_MULTIPLIER;
+
+ cagf = I915_READ(GEN6_RPSTAT1);
+ if (IS_HASWELL(dev) || IS_BROADWELL(dev))
+ cagf = (cagf & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
+ else
+ cagf = (cagf & GEN6_CAGF_MASK) >>
GEN6_CAGF_SHIFT;
+ cagf *= GT_FREQUENCY_MULTIPLIER;
+
+ seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x
IIR=0x%08x, MASK=0x%08x\n",
+ I915_READ(GEN6_PMIER),
+ I915_READ(GEN6_PMIMR),
+ I915_READ(GEN6_PMISR),
+ I915_READ(GEN6_PMIIR),
+ I915_READ(GEN6_PMINTRMSK));
+ seq_printf(m, "GT_PERF_STATUS: 0x%08x (ratio: %d, VID:
%d, limit: %d)\n",
+ gt_perf_status,
+ (gt_perf_status & 0xff00) >> 8,
+ gt_perf_status & 0xff,
+ rp_state_limits & 0xff);
+
+ max_freq = (rp_state_cap & 0xff0000) >> 16;
+ seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
+ max_freq * GT_FREQUENCY_MULTIPLIER);
+
+ max_freq = (rp_state_cap & 0xff00) >> 8;
+ seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
+ max_freq * GT_FREQUENCY_MULTIPLIER);
+
+ max_freq = rp_state_cap & 0xff;
+ seq_printf(m, "Max non-overclocked (RP0) frequency:
%dMHz\n",
+ max_freq * GT_FREQUENCY_MULTIPLIER);
+
+ seq_printf(m, "Max overclocked frequency: %dMHz\n",
+ dev_priv->rps.max_freq *
GT_FREQUENCY_MULTIPLIER);
+
+ seq_printf(m, "requested GPU freq: %d MHz\n", cagf);
+ seq_printf(m, "current GPU freq: %d MHz\n", reqf);
+ }
rpmodectl = I915_READ(GEN6_RP_CONTROL);
rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
- rpstat = I915_READ(GEN6_RPSTAT1);
- rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
+ rpupei = I915_READ(GEN6_RP_UP_EI);
+ rpcurupei = I915_READ(GEN6_RP_CUR_UP_EI);
rpcurup = I915_READ(GEN6_RP_CUR_UP);
rpprevup = I915_READ(GEN6_RP_PREV_UP);
- rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
+ rpdownei = I915_READ(GEN6_RP_DOWN_EI);
+ rpcurdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
- if (IS_HASWELL(dev) || IS_BROADWELL(dev))
- cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
- else
- cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
- cagf *= GT_FREQUENCY_MULTIPLIER;
gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
- mutex_unlock(&dev->struct_mutex);
- seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x,
MASK=0x%08x\n",
- I915_READ(GEN6_PMIER),
- I915_READ(GEN6_PMIMR),
- I915_READ(GEN6_PMISR),
- I915_READ(GEN6_PMIIR),
- I915_READ(GEN6_PMINTRMSK));
- seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
- seq_printf(m, "Render p-state ratio: %d\n",
- (gt_perf_status & 0xff00) >> 8);
- seq_printf(m, "Render p-state VID: %d\n",
- gt_perf_status & 0xff);
- seq_printf(m, "Render p-state limit: %d\n",
- rp_state_limits & 0xff);
- seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
- seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
- seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
- seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
- seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
- seq_printf(m, "CAGF: %dMHz\n", cagf);
- seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
+ seq_puts(m, "\n");
+ seq_printf(m, "RP CONTROL: 0x%08x\n", rpmodectl);
+ seq_printf(m, "RP UP EI: 0x%08x\n", rpupei);
+ seq_printf(m, "RP UP THRESHOLD: 0x%08x\n", rpinclimit);
+ seq_printf(m, "RP DOWN EI: 0x%08x\n", rpdownei);
+ seq_printf(m, "RP DOWN THRESHOLD: 0x%08x\n", rpdeclimit);
+ seq_printf(m, "RP CUR UP EI: %dus\n", rpcurupei &
GEN6_CURICONT_MASK);
seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
GEN6_CURBSYTAVG_MASK);
seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
GEN6_CURBSYTAVG_MASK);
- seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
+ seq_printf(m, "RP CUR DOWN EI: %dus\n", rpcurdownei &
GEN6_CURIAVG_MASK);
seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
GEN6_CURBSYTAVG_MASK);
seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
GEN6_CURBSYTAVG_MASK);
-
- max_freq = (rp_state_cap & 0xff0000) >> 16;
- seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
- max_freq * GT_FREQUENCY_MULTIPLIER);
-
- max_freq = (rp_state_cap & 0xff00) >> 8;
- seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
- max_freq * GT_FREQUENCY_MULTIPLIER);
-
- max_freq = rp_state_cap & 0xff;
- seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
- max_freq * GT_FREQUENCY_MULTIPLIER);
-
- seq_printf(m, "Max overclocked frequency: %dMHz\n",
- dev_priv->rps.max_freq * GT_FREQUENCY_MULTIPLIER);
- } else if (IS_VALLEYVIEW(dev)) {
- u32 freq_sts, val;
-
- mutex_lock(&dev_priv->rps.hw_lock);
- freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
- seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
- seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
-
- val = valleyview_rps_max_freq(dev_priv);
- seq_printf(m, "max GPU freq: %d MHz\n",
- vlv_gpu_freq(dev_priv, val));
-
- val = valleyview_rps_min_freq(dev_priv);
- seq_printf(m, "min GPU freq: %d MHz\n",
- vlv_gpu_freq(dev_priv, val));
-
- seq_printf(m, "current GPU freq: %d MHz\n",
- vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
- mutex_unlock(&dev_priv->rps.hw_lock);
- } else {
- seq_puts(m, "no P-state info available\n");
}
-out:
intel_runtime_pm_put(dev_priv);
- return ret;
+ return 0;
}
static int ironlake_drpc_info(struct seq_file *m)
--
2.0.1
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