On Thu, Jul 10, 2014 at 08:31:19PM +0100, Chris Wilson wrote: > We can eliminate a lot of special case code by making the computation of > the interrupt mask be correct for all callers. > > Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> > --- > drivers/gpu/drm/i915/intel_pm.c | 10 +++++----- > 1 file changed, 5 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 5c27065bac17..1302e1bc9136 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -3183,6 +3183,9 @@ static u32 gen6_rps_pm_mask(struct drm_i915_private > *dev_priv, u8 val) > if (val < dev_priv->rps.max_freq_softlimit) > mask |= GEN6_PM_RP_UP_THRESHOLD; > > + mask |= dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | > GEN6_PM_RP_UP_EI_EXPIRED); > + mask &= dev_priv->pm_rps_events;
Might as well move pm_rps_events to dev_priv->rps, too, next to the work item. Anyway, first 2 patches merged. -Daniel > + > /* IVB and SNB hard hangs on looping batchbuffer > * if GEN6_PM_UP_EI_EXPIRED is masked. > */ > @@ -3274,11 +3277,8 @@ static void vlv_set_rps_idle(struct drm_i915_private > *dev_priv) > > vlv_force_gfx_clock(dev_priv, false); > > - if (dev_priv->pm_rps_events & GEN6_PM_RP_UP_EI_EXPIRED) > - I915_WRITE(GEN6_PMINTRMSK, ~dev_priv->pm_rps_events); > - else > - I915_WRITE(GEN6_PMINTRMSK, > - gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq)); > + I915_WRITE(GEN6_PMINTRMSK, > + gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq)); > } > > void gen6_rps_idle(struct drm_i915_private *dev_priv) > -- > 2.0.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
