[Intel-wired-lan] [PATCH iwl-next v1 3/8] igc: refactor TXDCTL macros to use FIELD_PREP and GEN_MASK

[Faizal Rahim]

Refactor TXDCTL macro handling to use FIELD_PREP and GENMASK macros.
This prepares the code for adding a new TXDCTL priority field in an
upcoming patch.

Signed-off-by: Faizal Rahim <faizal.abdul.ra...@linux.intel.com>
---
 drivers/net/ethernet/intel/igc/igc.h      | 16 +++++++++++-----
 drivers/net/ethernet/intel/igc/igc_main.c |  6 ++----
 2 files changed, 13 insertions(+), 9 deletions(-)

diff --git a/drivers/net/ethernet/intel/igc/igc.h 
b/drivers/net/ethernet/intel/igc/igc.h
index bc37cc8deefb..4e44304b0608 100644
--- a/drivers/net/ethernet/intel/igc/igc.h
+++ b/drivers/net/ethernet/intel/igc/igc.h
@@ -487,16 +487,22 @@ static inline u32 igc_rss_type(const union 
igc_adv_rx_desc *rx_desc)
  */
 #define IGC_RX_PTHRESH                 8
 #define IGC_RX_HTHRESH                 8
-#define IGC_TXDCTL_PTHRESH             8
-#define IGC_TXDCTL_HTHRESH             1
 #define IGC_RX_WTHRESH                 4
-#define IGC_TXDCTL_WTHRESH             16
 
+#define IGC_TXDCTL_PTHRESH_MASK                GENMASK(4, 0)
+#define IGC_TXDCTL_HTHRESH_MASK                GENMASK(12, 8)
+#define IGC_TXDCTL_WTHRESH_MASK                GENMASK(20, 16)
+#define IGC_TXDCTL_QUEUE_ENABLE_MASK   GENMASK(25, 25)
+#define IGC_TXDCTL_SWFLUSH_MASK                GENMASK(26, 26)
+
+#define IGC_TXDCTL_PTHRESH(x)          FIELD_PREP(IGC_TXDCTL_PTHRESH_MASK, (x))
+#define IGC_TXDCTL_HTHRESH(x)          FIELD_PREP(IGC_TXDCTL_HTHRESH_MASK, (x))
+#define IGC_TXDCTL_WTHRESH(x)          FIELD_PREP(IGC_TXDCTL_WTHRESH_MASK, (x))
 /* Additional Transmit Descriptor Control definitions */
 /* Ena specific Tx Queue */
-#define IGC_TXDCTL_QUEUE_ENABLE        0x02000000
+#define IGC_TXDCTL_QUEUE_ENABLE                
FIELD_PREP(IGC_TXDCTL_QUEUE_ENABLE_MASK, 1)
 /* Transmit Software Flush */
-#define IGC_TXDCTL_SWFLUSH     0x04000000
+#define IGC_TXDCTL_SWFLUSH             FIELD_PREP(IGC_TXDCTL_SWFLUSH_MASK, 1)
 
 #define IGC_RX_DMA_ATTR \
        (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)
diff --git a/drivers/net/ethernet/intel/igc/igc_main.c 
b/drivers/net/ethernet/intel/igc/igc_main.c
index 725c8f0b9f3d..86716fabf6a9 100644
--- a/drivers/net/ethernet/intel/igc/igc_main.c
+++ b/drivers/net/ethernet/intel/igc/igc_main.c
@@ -749,11 +749,9 @@ static void igc_configure_tx_ring(struct igc_adapter 
*adapter,
        wr32(IGC_TDH(reg_idx), 0);
        writel(0, ring->tail);
 
-       txdctl |= IGC_TXDCTL_PTHRESH;
-       txdctl |= IGC_TXDCTL_HTHRESH << 8;
-       txdctl |= IGC_TXDCTL_WTHRESH << 16;
+       txdctl |= IGC_TXDCTL_PTHRESH(8) | IGC_TXDCTL_HTHRESH(1) |
+                 IGC_TXDCTL_WTHRESH(16) | IGC_TXDCTL_QUEUE_ENABLE;
 
-       txdctl |= IGC_TXDCTL_QUEUE_ENABLE;
        wr32(IGC_TXDCTL(reg_idx), txdctl);
 }
 
-- 
2.34.1