The ixgbe device registers/descriptors expect little-endian ordering. Make
the code aware that the e610 adapter operates on data with little endian
ordering. The extra conversion is required on big-endian hosts. In most
scenarios this conversion is not required.
Fixes: 46761fd52a88 ("ixgbe: Add support for E610 FW Admin Command Interface")
Reviewed-by: Aleksandr Loktionov <[email protected]>
Signed-off-by: Piotr Kwapulinski <[email protected]>
---
drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c
b/drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c
index c2f8189..f494e90 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c
@@ -113,7 +113,8 @@ static int ixgbe_aci_send_cmd_execute(struct ixgbe_hw *hw,
/* Descriptor is written to specific registers */
for (i = 0; i < IXGBE_ACI_DESC_SIZE_IN_DWORDS; i++)
- IXGBE_WRITE_REG(hw, IXGBE_PF_HIDA(i), raw_desc[i]);
+ IXGBE_WRITE_REG(hw, IXGBE_PF_HIDA(i),
+ le32_to_cpu(raw_desc[i]));
/* SW has to set PF_HICR.C bit and clear PF_HICR.SV and
* PF_HICR_EV
@@ -145,7 +146,7 @@ static int ixgbe_aci_send_cmd_execute(struct ixgbe_hw *hw,
if ((hicr & IXGBE_PF_HICR_SV)) {
for (i = 0; i < IXGBE_ACI_DESC_SIZE_IN_DWORDS; i++) {
raw_desc[i] = IXGBE_READ_REG(hw, IXGBE_PF_HIDA(i));
- raw_desc[i] = raw_desc[i];
+ raw_desc[i] = cpu_to_le32(raw_desc[i]);
}
}
@@ -153,7 +154,7 @@ static int ixgbe_aci_send_cmd_execute(struct ixgbe_hw *hw,
if ((hicr & IXGBE_PF_HICR_EV) && !(hicr & IXGBE_PF_HICR_C)) {
for (i = 0; i < IXGBE_ACI_DESC_SIZE_IN_DWORDS; i++) {
raw_desc[i] = IXGBE_READ_REG(hw, IXGBE_PF_HIDA_2(i));
- raw_desc[i] = raw_desc[i];
+ raw_desc[i] = cpu_to_le32(raw_desc[i]);
}
}
--
2.47.1
