From: Karol Kolacinski <[email protected]> Remove the PF_SB_REM_DEV_CTL register write from ice_ptp_init_phc_e82x(). PHY access is enabled by default on E82X devices and the driver does not need to configure switch device access. The register write was a remnant of an earlier SWITCH_MODE workaround for a FIFO issue and is no longer needed.
Also update the kernel-doc comment to refer to the E82X family rather than E822. Signed-off-by: Karol Kolacinski <[email protected]> Signed-off-by: Aleksandr Loktionov <[email protected]> --- drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 13 ++----------- 1 file changed, 2 insertions(+), 11 deletions(-) diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c index 61c0a0d..7b1b402 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c +++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c @@ -2767,22 +2767,13 @@ static int ice_ptp_set_vernier_wl(struct ice_hw *hw) } /** - * ice_ptp_init_phc_e82x - Perform E822 specific PHC initialization + * ice_ptp_init_phc_e82x - Perform E82X specific PHC initialization * @hw: pointer to HW struct * - * Perform PHC initialization steps specific to E822 devices. + * Perform PHC initialization steps specific to E82X devices. */ static int ice_ptp_init_phc_e82x(struct ice_hw *hw) { - u32 val; - - /* Enable reading switch and PHY registers over the sideband queue */ -#define PF_SB_REM_DEV_CTL_SWITCH_READ BIT(1) -#define PF_SB_REM_DEV_CTL_PHY0 BIT(2) - val = rd32(hw, PF_SB_REM_DEV_CTL); - val |= (PF_SB_REM_DEV_CTL_SWITCH_READ | PF_SB_REM_DEV_CTL_PHY0); - wr32(hw, PF_SB_REM_DEV_CTL, val); - /* Set window length for all the ports */ return ice_ptp_set_vernier_wl(hw); } -- 2.52.0
