From: "Jason-JH.Lin" <jason-jh....@mediatek.com>
Add gce node and gce alias to mt8195 device tree.
Signed-off-by: Jason-JH.Lin <jason-jh....@mediatek.com>
Signed-off-by: Tinghan Shen <tinghan.s...@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index cb2b79dc08d1..724c6ca837b6 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -6,6 +6,7 @@
/dts-v1/;
#include <dt-bindings/clock/mt8195-clk.h>
+#include <dt-bindings/gce/mt8195-gce.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/memory/mt8195-memory-port.h>
@@ -19,6 +20,11 @@
#address-cells = <2>;
#size-cells = <2>;
+ aliases {
+ gce0 = &gce0;
+ gce1 = &gce1;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -739,6 +745,22 @@
#iommu-cells = <1>;
};
+ gce0: mailbox@10320000 {
+ compatible = "mediatek,mt8195-gce";
+ reg = <0 0x10320000 0 0x4000>;
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>;
+ #mbox-cells = <2>;
+ clocks = <&infracfg_ao CLK_INFRA_AO_GCE>;
+ };
+
+ gce1: mailbox@10330000 {
+ compatible = "mediatek,mt8195-gce";
+ reg = <0 0x10330000 0 0x4000>;
+ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH 0>;
+ #mbox-cells = <2>;
+ clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>;
+ };
+
scp: scp@10500000 {
compatible = "mediatek,mt8195-scp";
reg = <0 0x10500000 0 0x100000>,
--
2.18.0
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