On Mon, 2022-07-04 at 12:44 +0200, AngeloGioacchino Del Regno wrote:
> Il 04/07/22 12:00, Tinghan Shen ha scritto:
> > From: "Jason-JH.Lin" <jason-jh....@mediatek.com>
> >
> > Add display node for vdosys0 of mt8195.
> >
> > Signed-off-by: Jason-JH.Lin <jason-jh....@mediatek.com>
> > Signed-off-by: Tinghan Shen <tinghan.s...@mediatek.com>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8195.dtsi | 109 +++++++++++++++++++++++
> > 1 file changed, 109 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > index 724c6ca837b6..faea8ef33e5a 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > @@ -1961,6 +1961,7 @@
> > vdosys0: syscon@1c01a000 {
> > compatible = "mediatek,mt8195-mmsys", "syscon";
> > reg = <0 0x1c01a000 0 0x1000>;
> > + mboxes = <&gce0 0 CMDQ_THR_PRIO_4>;
> > #clock-cells = <1>;
> > };
> >
> > @@ -1976,6 +1977,114 @@
> > power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
> > };
> >
> > + ovl0: ovl@1c000000 {
> > + compatible = "mediatek,mt8195-disp-ovl",
> > + "mediatek,mt8183-disp-ovl";
>
> This fits in one line, please fix, here and all of the other instances of
> that.
>
> > + reg = <0 0x1c000000 0 0x1000>;
> > + interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>;
> > + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
> > + clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>;
> > + iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>;
> > + mediatek,gce-client-reg =
> > + <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>;
>
> Same for gce-client-reg.
>
> Regards,
> Angelo
Ok, I'll update in next version.
Thanks,
TingHan
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