Hi,

On 9/5/18 8:28 PM, Giovani Gracioli wrote:
> Yes, I did enable with Erika API.

No, I meant if you tried to receive the SGI via Jailhouse inmates. I
don't know Erika internals.

Some test like:

diff --git a/inmates/demos/arm/gic-demo.c b/inmates/demos/arm/gic-demo.c
index b2246deb..86be1b1e 100644
--- a/inmates/demos/arm/gic-demo.c
+++ b/inmates/demos/arm/gic-demo.c
@@ -35,6 +35,8 @@ static void handle_IRQ(unsigned int irqn)

        if (irqn != TIMER_IRQ)
                return;
+       else
+               printk("Hey, there's some IRQ %u\n", irqn);

        delta = timer_get_ticks() - expected_ticks;
        if (delta < min_delta)
@@ -59,6 +61,7 @@ void inmate_main(void)
        printk("Initializing the GIC...\n");
        gic_setup(handle_IRQ);
        gic_enable_irq(TIMER_IRQ);
+       gic_enable_irq(15);

        printk("Initializing the timer...\n");
        ticks_per_beat = timer_get_frequency() / BEATS_PER_SEC;



Thanks
  Ralf

> 
> s |= CreateTask( &isr_ivshmem, OSEE_TASK_TYPE_ISR2, handle_IRQ, 1U, 1U, 1U, 
> OSEE_SYSTEM_STACK );
> 
> SetISR2Source(isr_ivshmem, i);
> gic_enable_irq(i); //this is actually from jailhouse api
> 
> Where "i" is the interrupt number. I tried having "i" with 15. Maybe 
> something in Erika is different. I will try with the gic-demo as well.
> 
>>> Hi,
>>>
>>> I am playing around IPI among non-root cells (I know it breaks the 
>>> isolation among cells, but I would like to understand the steps). I forced 
>>> a call to irqchip_set_pending from CPU 3 to CPU 2 in the 
>>> gic_handle_sgir_write() function:
>>>
>>> irqchip_set_pending(per_cpu(2), sgi->id);
>>>
>>> sgi->id is 15. I can see that CPU 2 receives the IPI:
>>>
>>> CPU 2 received an SGI 0
>>> irqchip_inject_pending irq_id = 15, sender 3
>>> gicv2_inject_irq() sender = 3, irq_id = 15
>>> CPU 2 writing 268438543 to lr reg (first_free = 0)
>>>
>>> However, the non-root cell does not receive the IPI (I am running Erika on 
>>> it).
>>
>> Did you try to receive the SGI in the gic-demo? You only have to
>> instrument handle_IRQ and enable the interrupt.
>>
>>   Ralf
>>
>>>
>>> I do not know in which IRQ number the SGI ID 15 is mapped to. What is the 
>>> relation of pin_base and pin_bitmap from the config file with SGIs? What 
>>> value should I write in the irqchips config?
>>>
>>> Best
>>> Giovani
>>>
> 

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