Author: robhamerling
Date: Sat Jun 6 07:59:54 2009
New Revision: 1033
Modified:
trunk/doc/html/devicefiles.html
Log:
Some textual enhancements
Modified: trunk/doc/html/devicefiles.html
==============================================================================
--- trunk/doc/html/devicefiles.html (original)
+++ trunk/doc/html/devicefiles.html Sat Jun 6 07:59:54 2009
@@ -212,7 +212,7 @@
enable_digital_io() -- disable analog module(s)
- var volatile bit led is pin_A1 -- define alias for pin_A1
+ var volatile bit led is pin_A1 -- declare alias for pin_A1
var volatile bit led_direction is pin_A1_direction
led_direction = output -- make LED-pin output
@@ -240,7 +240,7 @@
Therefore it is possible that some names may not be conform the datasheet.
When you find such a deviation, please report to the Jallib team!
-<p>For all registers of the chip a name is defined and where appropriate
+<p>For all registers of the chip a name is declared and where appropriate
also the individual bits or groups of bits are declared.
Also some aliases are declared for easy the migration or conversion of
existing JalV2 libraries and programs to the Jallib environment.
@@ -257,15 +257,13 @@
<h3>PORTx and TRISx</h3>
-<p>For all ports and port pins a device independent alias is defined and a
-similar direction definition, as the following examples show:
+<p>For all ports and port pins a device independent alias is declared and a
+similar direction declaration, as the following examples show:
<pre>
var volatile byte PORTA at <addr>
- var byte PORTA_low -- low order nibble
- var byte PORTA_high -- high order nibble
- var volatile bit pin_A0 at PORTA : 0
var volatile byte TRISA at <addr>
var volatile byte PORTA_direction at TRISA
+ var volatile bit pin_A0 at PORTA : 0
var volatile bit pin_A0_direction at TRISA : 0
</pre>
<p>etc. (for all other existing pins and ports)
@@ -277,18 +275,16 @@
<pre>
var volatile byte GPIO at <addr>
var volatile byte PORTA at GPIO
- var byte PORTA_low -- low order nibble
- var byte PORTA_high -- high order nibble
- var volatile bit pin_A0 at GPIO : 0
var volatile byte TRISIO at <addr>
var volatile byte TRISA at TRISIO
var volatile byte PORTA_direction at TRISIO
+ var volatile bit pin_A0 at GPIO : 0
var volatile bit pin_A0_direction at TRISIO : 0
</pre>
<p>etc. (for all other existing pins)
<h3>Non-memory-mapped registers</h3>
-<p>Some PICs, especially in the baseline series, are missing some
+<p>Some PICs, mainly in the baseline series, are missing some
addressable ('memory mapped') registers.
For example the 12-bit core PICs (10Fs, 12F5x, etc) have no memory
mapped TRISx registers, in stead these PICs have TRISx instructions to
@@ -309,7 +305,7 @@
<h3>Nibbles</h3>
<p>Since frequently the upper and lower 4 bits ('nibble') of a port are
-used as a unit, these are defined as pseudo variables.
+used as a unit, these are declared as pseudo variables.
<pre>
PORTx_low - bits 0..3
PORTx_high - bits 4..7
@@ -639,7 +635,7 @@
<h3>Memory allocation</h3>
<p>The device files specify the amounts of available shared and unshared
-memory (RAM, gpr) in bytes.
+memory (RAM, GPR) in bytes.
<p>For user program memory (variables, constants) the compiler allocates
memory first in unshared RAM then in shared RAM.
Some specific compiler 'internally' used bytes can be and should
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