On 04/15/10 04:04 pm, m...@watty wrote:
on 18F4550 we have pragma target USBPLL F48MHZ there is no such pragma on the 18F67J50,
The J series have fewer configuration bytes in general, and because these are part of program memory many bits are reserved (1) to make the words behave like NOPs when accidently invoked.
Yet if you are using external crystal, PLL, and High speed USB, the pdf datasheets look very similar. I looked at the datasheet for clock setup on both PIC and the jal device files, and I could not figure what pragma target USBPLL F48MHZ is for, or if it's important why it's not on 18FxxJxx
I suppose because of limited config bits some configurable options of the 18f4550 are fixed with the 18f67j50.
BTW The 'programming specifications' have generally a more extensive description of the configuration bits (I have not checked for this case).
Regards, Rob. -- Rob Hamerling, Vianen, NL (http://www.robh.nl/) -- You received this message because you are subscribed to the Google Groups "jallib" group. To post to this group, send email to [email protected]. To unsubscribe from this group, send email to [email protected]. For more options, visit this group at http://groups.google.com/group/jallib?hl=en.
