Hi Eur,
On 08/05/10 01:37 pm, Eur van Andel wrote:
Log: Updated samples which reference timer0 bits in OPTION_REG
These references are replaced by T0CON aliases.
Makes it easier to migrate these samples to 18F series
(where these aliases are meant for).
Does T0CON have the same bit placements as OPTION_REG?
I haven't checked all (18F) PICs, but did some random checks
from which I concluded 'yes'.
rtc_isr_tmr0.jal is still in assembler.
OPTION_REG nor T0CON are referenced in the ISR, so I don't see any danger.
Should I update it to JALV2? I made a new rtc with tmr3,
> which is almost the same.
I would say yes, please.
I may not have the hardware to test all the samples though. Should I
make a new file, like rtc_isr_tmr0_no_asm.jal?
When the functionality of the JALV2 version would be exactly the same as
the current ASM version, then why not simply replace it? For safety you
could rename the old lib (e.g. rtc_isr_tmr0_asm.jal or put it temporary
aside (in casualties?), and delete it when the new one has proven to be OK.
The samples are for only 3 different popular PICS. If needed I think I
could do some tests for you.
Regards, Rob.
--
Rob Hamerling, Vianen, NL (http://www.robh.nl/)
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