On Thu, Aug 5, 2010 at 6:39 AM, Rob Hamerling <[email protected]>wrote:
> > Hi Eur, > > > On 08/05/10 01:37 pm, Eur van Andel wrote: > > Log: Updated samples which reference timer0 bits in OPTION_REG >>> These references are replaced by T0CON aliases. >>> Makes it easier to migrate these samples to 18F series >>> (where these aliases are meant for). >>> >> >> Does T0CON have the same bit placements as OPTION_REG? >> > > I haven't checked all (18F) PICs, but did some random checks > from which I concluded 'yes'. > > > rtc_isr_tmr0.jal is still in assembler. >> > > OPTION_REG nor T0CON are referenced in the ISR, so I don't see any danger. > > > Should I update it to JALV2? I made a new rtc with tmr3, >> > > which is almost the same. > > I would say yes, please. > > > I may not have the hardware to test all the samples though. Should I >> make a new file, like rtc_isr_tmr0_no_asm.jal? >> > > When the functionality of the JALV2 version would be exactly the same as > the current ASM version, then why not simply replace it? The assembler version will work with lower timings than the jal versions. If your purpose is creating a library only for 1s timer, then replacing with jal is OK. But if you want a precisely time base from say 1mS to 1S, then switching to jal will probably make that bressenham library unusefull. Vasile -- You received this message because you are subscribed to the Google Groups "jallib" group. To post to this group, send email to [email protected]. To unsubscribe from this group, send email to [email protected]. For more options, visit this group at http://groups.google.com/group/jallib?hl=en.
