Asr1000 line are solid if needed for nat -- Payam Chychi Solution Architect
On Monday, November 30, 2015 at 5:57 AM, Saku Ytti wrote: > On 30 November 2015 at 15:39, Adam Vitkovsky <adam.vitkov...@gamma.co.uk> > wrote: > > Hey Adam, > > > I think this can be alleviated with BGP provider edge link protection(Cisco > > BGP PIC Edge)/BGP PIC Edge(Cisco BGP PIC Core). > > However in Junos this is available only for VRFs. > > > > > You'll be happy to hear it got into 15.1 for INET \o/ > > > That's right Trio's LU is just better, it can cope with any combination of > > features enabled with only small performance hit compared to A9k's NPU. > > However if QX chip is used the whole LU performance advantage is > > jeopardized (but at least the degradation is deterministic). > > > > > My main woe is not feature parity or inherent capability of > Trio/EZ/nPower, it's more that once JNPR ships something, it'll work > on all Trio kit. Cisco is coming up _really_ good troubleshooting > tooling for ASR9k, but they'll arrive at different pace (or maybe not > at all) at different engines, which is completely understandable for > this low-level stuff. > > > Also the basic Junos documentation is incomplete and getting some deep > > level information is next to impossible. > > ACK. This is not mentioned often enough, Cisco is doing pretty good > job in documents. > > > And what about ASR903 it's very similar product to MX104. > > Dunno, I'd say it's more similar to ACX1k, both are running BRCM > Enduro? Looking forward to Waris' webinar. > > -- > ++ytti > _______________________________________________ > juniper-nsp mailing list juniper-nsp@puck.nether.net > https://puck.nether.net/mailman/listinfo/juniper-nsp > > _______________________________________________ juniper-nsp mailing list juniper-nsp@puck.nether.net https://puck.nether.net/mailman/listinfo/juniper-nsp
