On Tue, Feb 19, 2013 at 10:18 PM, horseriver <[email protected]> wrote:
> On Mon, Feb 18, 2013 at 12:25:43PM +0000, Anuz Pratap Singh Tomar wrote: > > On Mon, Feb 18, 2013 at 1:55 AM, horseriver <[email protected]> > wrote: > > > > > Intel® 64 and IA-32 Architectures > > Software Developer’s Manual > > Volume 3A: > > System Programming Guide, Part 1 > > page 65 > > > > The linear address of the base of the GDT is contained in the GDT > register > > (GDTR); > > the linear address of the LDT is contained in the LDT register (LDTR). > > > > Thanks! > > As the value is a linear address , so when load an segment descriptor > from an address , > such as lss ubstruction: lss 0x10023,%esp , cpu will check to make sure > this stack descriptor > exist in gdt . > So , we will get a linear address by the gdtr value and the > descriptor's index , then *if this linear address* > has not phisical page mapped , it will cause a pagefault trap.then ,how > to resolve this trap? > > > Please use reply all or add kernelnewbies to CC I am not very sure of how this trap will be resolved, but you can have a look at this: Understanding Linux Kernel Section 9.4 http://www.makelinux.net/books/ulk3/understandlk-CHP-9-SECT-4 > > > > > However for 32 bit registers, this document provides some details in > > protected mode: > > > > http://home.swipnet.se/smaffy/asm/info/PMODEDetailedApproach.txt > > > > > > > > > thanks! > > > > > > _______________________________________________ > > > Kernelnewbies mailing list > > > [email protected] > > > http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies > > > > > > > > > > > -- > > Thank you > > Warm Regards > > Anuz > -- Thank you Warm Regards Anuz
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