Avi Kivity wrote:
> The pte is stored/cached in two different places (in addition to what 
> Linux already knows about):
> 
> - in the shadow page tables
> - in the tlbs of the vcpus that may have referenced the page
> 
> so, when swapping out the page, you need to use the kvm rmap to find all 
> shadow ptes which reference the page, and also IPI every processor that 
> is running a vcpu belonging to the same virtual machine.
> 
> You also need to extend kvm rmap to contain read-only pages (as this 
> patchset does).  That's a cost that may have a serious performance impact.
Very interresting. Thank you for explaining this.

> s390 uses the same pte for userspace virtual and guest physical?  that 
> explains why a single invalidate suffices for both.  But aren't guest 
> virtual translations cached in the tlb as well?
Yes, we use the same pte for both. We also use the same tlb entries 
for both userspace access and guest mode. This way, we don't need to 
invalidate them when entering or exiting the vm context.

> An example: suppose host pfn 7 is allocated as guest pfn 8 (and 
> therefore, userspace address 0x8000).  Suppose further the guest maps 
> guest pfn 8 to guest virtual 0x10000 and guest virtal 0x11000.  Aren't 
> there three tlbs you need to shoot down?  host virtual 0x8000->pfn 7 and 
> guest virual 0x10000->pfn 7 and 0x11000->pfn 7?
So far, we have a 1:1 mapping between guest physical and host 
userspace. A userspace pointer equals a guest real pointer.
Our hardware control block for vcpu also allows to set an offset 
"guest physical + offset = host user". The CPU knows about this offset 
when doing page translations, and this is also transparent with regard 
to tlb entries.
Now if the guest itself enables dynamic address translation, the tlb 
entry can cache information about both page translation steps. This 
process is transparent for both guest and host operating system. If 
the host flushes this tlb entry, the information about the guest 
internal translation is also removed.

so long,
Carsten

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