On Sun, Jan 27, 2008 at 10:52:30AM +0200, Avi Kivity wrote:
> Joerg Roedel wrote:
> > This patch contains the SVM architecture dependent changes for KVM to enable
> > support for the Nested Paging feature of AMD Barcelona and Phenom
> > processors.
> >
> > +#ifdef CONFIG_X86_64
> > +static bool npt_enabled = true;
> > +#else
> > static bool npt_enabled = false;
> > +#endif
> >
>
> I think that i386 + pae can also support npt, with no changes, no?
>
> So we should check CONFIG_X86_PAE, not X86_64.
Yes, I think that too. But its completly untested so I disabled it for
the first post of this patchset.
> > +
> > + if (npt_enabled) {
> > + /* Setup VMCB for Nested Paging */
> > + control->nested_ctl = 1;
> > + control->intercept_exceptions &= ~(1 << PF_VECTOR);
> > + control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
> > + INTERCEPT_CR3_MASK|
> > + INTERCEPT_CR4_MASK);
> > + control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
> > + INTERCEPT_CR3_MASK|
> > + INTERCEPT_CR4_MASK);
> >
>
> What happens to lazy fpu if we don't trap cr0 changes?
>
> Perhaps it's worth disabling lazy fpu with npt.
It should be implicitly disabled with npt because accesses to cr3 are
not intercepted anymore. The svm_set_cr3 function is the only place
which disables fpu switching.
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