Am 27.11.2012 06:32, schrieb Will Auld: > CPUID.7.0.EBX[1]=1 indicates IA32_TSC_ADJUST MSR 0x3b is supported > > Basic design is to emulate the MSR by allowing reads and writes to the > hypervisor vcpu specific locations to store the value of the emulated MSRs. > In this way the IA32_TSC_ADJUST value will be included in all reads to > the TSC MSR whether through rdmsr or rdtsc. > > As this is a new MSR that the guest may access and modify its value needs > to be migrated along with the other MRSs. The changes here are specifically > for recognizing when IA32_TSC_ADJUST is enabled in CPUID and code added > for migrating its value. > > Signed-off-by: Will Auld <will.a...@intel.com>
Reviewed-by: Andreas Färber <afaer...@suse.de> from the CPU perspective. Thanks, Andreas -- SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
