On Fri, Jun 07, 2013 at 10:31:38AM +0800, Arthur Chunqi Li wrote:
> Add a function trap_emulator to run an instruction in emulator.
> Set inregs first (%rax, %rsp, %rbp, %rflags have special usage and
> cannot set in inregs), put instruction codec in alt_insn and call
> func with alt_insn_length. Get results in outregs.
>
Why %rax, %rsp, %rbp, %rflags cannot be set in inregs?
%rax because trapping instruction uses it? Use one that does not use
register at all: MOV r/m32, imm32
%rsp and %rbp because of ret on instruction page? Use the same trick
realmode.c test uses: have the code that sets/saves registers in
insn_page/alt_insn_page itself and copy the instruction you want to test
into the page itself instead of doing call.
Not sure what is so special about %rflags.
> Signed-off-by: Arthur Chunqi Li <yzt...@gmail.com>
> ---
> x86/emulator.c | 67
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 67 insertions(+)
> mode change 100644 => 100755 x86/emulator.c
>
> diff --git a/x86/emulator.c b/x86/emulator.c
> old mode 100644
> new mode 100755
> index 96576e5..770e8f7
> --- a/x86/emulator.c
> +++ b/x86/emulator.c
> @@ -11,6 +11,13 @@ int fails, tests;
>
> static int exceptions;
>
> +struct regs {
> + u64 rax, rbx, rcx, rdx;
> + u64 rsi, rdi, rsp, rbp;
> + u64 rip, rflags;
> +};
> +static struct regs inregs, outregs;
> +
> void report(const char *name, int result)
> {
> ++tests;
> @@ -685,6 +692,66 @@ static void test_shld_shrd(u32 *mem)
> report("shrd (cl)", *mem == ((0x12345678 >> 3) | (5u << 29)));
> }
>
> +static void trap_emulator(uint64_t *mem, uint8_t *insn_page,
> + uint8_t *alt_insn_page, void *insn_ram,
> + uint8_t *alt_insn, int alt_insn_length)
> +{
> + ulong *cr3 = (ulong *)read_cr3();
> + int i;
> + static struct regs save;
> +
> + // Pad with RET instructions
> + memset(insn_page, 0xc3, 4096);
> + memset(alt_insn_page, 0xc3, 4096);
> +
> + // Place a trapping instruction in the page to trigger a VMEXIT
> + insn_page[0] = 0x89; // mov %eax, (%rax)
> + insn_page[1] = 0x00;
> + insn_page[2] = 0x90; // nop
> + insn_page[3] = 0xc3; // ret
> +
> + // Place the instruction we want the hypervisor to see in the alternate
> page
> + for (i=0; i<alt_insn_length; i++)
> + alt_insn_page[i] = alt_insn[i];
> + save = inregs;
> +
> + // Load the code TLB with insn_page, but point the page tables at
> + // alt_insn_page (and keep the data TLB clear, for AMD decode assist).
> + // This will make the CPU trap on the insn_page instruction but the
> + // hypervisor will see alt_insn_page.
> + install_page(cr3, virt_to_phys(insn_page), insn_ram);
> + invlpg(insn_ram);
> + // Load code TLB
> + asm volatile("call *%0" : : "r"(insn_ram + 3));
> + install_page(cr3, virt_to_phys(alt_insn_page), insn_ram);
> + // Trap, let hypervisor emulate at alt_insn_page
> + asm volatile(
> + "xchg %%rbx, 8+%[save] \n\t"
> + "xchg %%rcx, 16+%[save] \n\t"
> + "xchg %%rdx, 24+%[save] \n\t"
> + "xchg %%rsi, 32+%[save] \n\t"
> + "xchg %%rdi, 40+%[save] \n\t"
> +
> + "call *%1\n\t"
> +
> + "mov %%rax, 0+%[save] \n\t"
> + "xchg %%rbx, 8+%[save] \n\t"
> + "xchg %%rcx, 16+%[save] \n\t"
> + "xchg %%rdx, 24+%[save] \n\t"
> + "xchg %%rsi, 32+%[save] \n\t"
> + "xchg %%rdi, 40+%[save] \n\t"
> + "mov %%rsp, 48+%[save] \n\t"
> + "mov %%rbp, 56+%[save] \n\t"
> + /* Save RFLAGS in outregs*/
> + "pushf \n\t"
> + "popq 72+%[save] \n\t"
> + : [save]"+m"(save)
> + : "r"(insn_ram), "a"(mem)
> + : "memory", "cc"
> + );
> + outregs = save;
> +}
> +
> static void advance_rip_by_3_and_note_exception(struct ex_regs *regs)
> {
> ++exceptions;
> --
> 1.7.9.5
--
Gleb.
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